forked from OSchip/llvm-project
[AMDGPU] Update mfma test to run gfx940 checks. NFC.
This commit is contained in:
Stanislav Mekhanoshin
parent
4609f60ebc
commit
631a643940
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@ -1,6 +1,7 @@
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; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,NOLIT-SRCC,GFX908,GFX908_A %s
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; RUN: llc -march=amdgcn -mcpu=gfx908 -mattr=-mfma-inline-literal-bug -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,LIT-SRCC,GFX908,GFX908_A %s
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; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX90A,GFX908_A %s
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; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX90A,GFX908_A,GFX90A_40 %s
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; RUN: llc -march=amdgcn -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GFX940,GFX90A_40 %s
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declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32, i32, i32)
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declare <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float, float, <16 x float>, i32, i32, i32)
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@ -54,7 +55,9 @@ declare i32 @llvm.amdgcn.workitem.id.x()
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; GFX908_A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX908_A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX908_A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-32:v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_f32_32x32x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_f32_32x32x1_2b_f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-4: v_accvgpr_read_b32
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; GFX908-COUNT-2: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}]
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; GFX908-COUNT-4: v_accvgpr_read_b32
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@ -78,7 +81,9 @@ bb:
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; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
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; GCN: s_load_dwordx16
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; GFX908_A-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_f32_16x16x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_f32_16x16x1_4b_f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT: v_accvgpr_read_b32
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; GFX908-COUNT-4: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}]
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -96,7 +101,9 @@ bb:
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; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
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; GCN: s_load_dwordx4
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; GFX908_A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_f32_4x4x1f32 [[RES:a\[[0-9]+:[0-9]+\]]], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_f32_4x4x1_16b_f32 [[RES:a\[[0-9]+:[0-9]+\]]], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-4: v_accvgpr_read_b32
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; GFX908: global_store_dwordx4
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -114,7 +121,9 @@ bb:
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; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
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; GCN: s_load_dwordx16
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; GFX908_A-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_f32_32x32x2f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_f32_32x32x2_f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-16: v_accvgpr_read_b32
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; GFX908-COUNT-4: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}]
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -132,7 +141,9 @@ bb:
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; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
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; GCN: s_load_dwordx4
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; GFX908_A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_f32_16x16x4f32 [[RES:a\[[0-9]+:[0-9]+\]]], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_f32_16x16x4_f32 [[RES:a\[[0-9]+:[0-9]+\]]], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-4: v_accvgpr_read_b32
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; GFX908: global_store_dwordx4
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -149,7 +160,9 @@ bb:
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; GCN-DAG: s_load_dwordx16
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; GCN-DAG: s_load_dwordx16
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; GFX908_A-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_f32_32x32x4f16 a[{{[0-9]+:[0-9]+}}], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_f32_32x32x4_2b_f16 a[{{[0-9]+:[0-9]+}}], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-32: v_accvgpr_read_b32
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; GFX908: global_store_dwordx4
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -168,7 +181,9 @@ bb:
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; GCN-LABEL: {{^}}test_mfma_f32_16x16x4f16:
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; GCN: s_load_dwordx16
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; GFX908_A-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_f32_16x16x4f16 a[{{[0-9]+:[0-9]+}}], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_f32_16x16x4_4b_f16 a[{{[0-9]+:[0-9]+}}], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-16: v_accvgpr_read_b32
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; GFX908: global_store_dwordx4
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -188,7 +203,9 @@ bb:
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; GCN: s_load_dwordx4
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; GCN: s_load_dwordx4
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; GFX908_A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_f32_4x4x4f16 [[RES:a\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_f32_4x4x4_16b_f16 [[RES:a\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-4: v_accvgpr_read_b32
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; GFX908: global_store_dwordx4
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -209,7 +226,9 @@ bb:
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; GCN: s_waitcnt lgkmcnt(0)
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; GFX908_A: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_f32_32x32x8f16 a[{{[0-9]+:[0-9]+}}], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_f32_32x32x8_f16 a[{{[0-9]+:[0-9]+}}], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-16: v_accvgpr_read_b32
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; GFX908: global_store_dwordx4
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -229,7 +248,9 @@ bb:
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; GCN: s_load_dwordx4
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; GCN: s_load_dwordx4
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; GFX908_A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_f32_16x16x16f16 [[RES:a\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_f32_16x16x16_f16 [[RES:a\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-4: v_accvgpr_read_b32
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; GFX908: global_store_dwordx4
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -282,7 +303,9 @@ bb:
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; GFX908_A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX908_A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX908_A-DAG: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-32: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_i32_32x32x4i8 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_i32_32x32x4_2b_i8 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-32: v_accvgpr_read_b32
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; GFX908: global_store_dwordx4
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -300,7 +323,9 @@ bb:
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; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
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; GCN: s_load_dwordx16
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; GFX908_A-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_i32_16x16x4i8 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_i32_16x16x4_4b_i8 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-16: v_accvgpr_read_b32
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; GFX908: global_store_dwordx4
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -318,7 +343,9 @@ bb:
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; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
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; GCN: s_load_dwordx4
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; GFX908_A-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
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; GFX940-COUNT-4: v_accvgpr_write_b32 a{{[0-9]+}}, s{{[0-9]+}}
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; GFX908_A: v_mfma_i32_4x4x4i8 [[RES:a\[[0-9]+:[0-9]+\]]], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX940: v_mfma_i32_4x4x4_16b_i8 [[RES:a\[[0-9]+:[0-9]+\]]], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
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; GFX908-COUNT-4: v_accvgpr_read_b32
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; GFX908: global_store_dwordx4
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -334,6 +361,8 @@ bb:
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; GCN-LABEL: {{^}}test_mfma_f32_32x32x1f32_forward_acc:
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; GFX908_A: v_mfma_f32_32x32x1f32 [[MAI1:a\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, v{{[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
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; GFX908_A-NEXT: v_mfma_f32_32x32x1f32 a[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, [[MAI1]]
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; GFX940: v_mfma_f32_32x32x1_2b_f32 [[MAI1:a\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, v{{[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
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; GFX940-NEXT: v_mfma_f32_32x32x1_2b_f32 a[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, [[MAI1]]
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define amdgpu_kernel void @test_mfma_f32_32x32x1f32_forward_acc(<32 x float> addrspace(1)* %arg) #0 {
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bb:
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%in.1 = load <32 x float>, <32 x float> addrspace(1)* %arg
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@ -346,6 +375,8 @@ bb:
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; GCN-LABEL: {{^}}test_mfma_f32_16x16x1f32_forward_acc:
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; GFX908_A: v_mfma_f32_16x16x1f32 [[MAI1:a\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, v{{[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
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; GFX908_A-NEXT: v_mfma_f32_16x16x1f32 a[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, [[MAI1]]
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; GFX940: v_mfma_f32_16x16x1_4b_f32 [[MAI1:a\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, v{{[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
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; GFX940-NEXT: v_mfma_f32_16x16x1_4b_f32 a[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, [[MAI1]]
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define amdgpu_kernel void @test_mfma_f32_16x16x1f32_forward_acc(<16 x float> addrspace(1)* %arg) #0 {
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bb:
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%in.1 = load <16 x float>, <16 x float> addrspace(1)* %arg
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; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32_forward_acc:
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; GFX908_A: v_mfma_f32_4x4x1f32 [[MAI1:a\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, v{{[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
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; GFX908_A-NEXT: v_mfma_f32_4x4x1f32 a[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, [[MAI1]]
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; GFX940: v_mfma_f32_4x4x1_16b_f32 [[MAI1:a\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, v{{[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
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; GFX940-NEXT: v_mfma_f32_4x4x1_16b_f32 a[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, v{{[0-9]+}}, [[MAI1]]
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define amdgpu_kernel void @test_mfma_f32_4x4x1f32_forward_acc(<4 x float> addrspace(1)* %arg) #0 {
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bb:
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%in.1 = load <4 x float>, <4 x float> addrspace(1)* %arg
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; NOLIT-SRCC: v_mfma_f32_4x4x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9:]+}}]
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; LIT-SRCC: v_mfma_f32_4x4x1f32 [[RES:a\[[0-9]+:[0-9]+\]]], [[ONE]], [[TWO]], 1.0
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; GFX90A: v_mfma_f32_4x4x1f32 [[RES:a\[[0-9]+:[0-9]+\]]], [[ONE]], [[TWO]], 1.0
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; GFX940: v_mfma_f32_4x4x1_16b_f32 [[RES:a\[[0-9]+:[0-9]+\]]], [[ONE]], [[TWO]], 1.0
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; GFX908-COUNT-4: v_accvgpr_read_b32
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; GFX908: global_store_dwordx4
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; GFX90A-NOT: v_accvgpr_read_b32
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@ -395,6 +429,7 @@ bb:
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; NOLIT-SRCC: v_mfma_f32_16x16x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9:]+}}]
|
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; LIT-SRCC: v_mfma_f32_16x16x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], 1.0
|
||||
; GFX90A: v_mfma_f32_16x16x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], 1.0
|
||||
; GFX940: v_mfma_f32_16x16x1_4b_f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], 1.0
|
||||
; GFX908-COUNT-16: v_accvgpr_read_b32
|
||||
; GFX908: global_store_dwordx4
|
||||
; GFX90A-NOT: v_accvgpr_read_b32
|
||||
|
|
@ -413,6 +448,7 @@ bb:
|
|||
; NOLIT-SRCC: v_mfma_f32_32x32x8f16 a[{{[0-9]+:[0-9]+}}], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}], a[{{[0-9:]+}}]
|
||||
; LIT-SRCC: v_mfma_f32_32x32x8f16 a[{{[0-9]+:[0-9]+}}], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}], 1.0
|
||||
; GFX90A: v_mfma_f32_32x32x8f16 a[{{[0-9]+:[0-9]+}}], v[[[ONE]]:{{[0-9]+}}], v[[[TWO]]:{{[0-9]+}}], 1.0
|
||||
; GFX940: v_mfma_f32_32x32x8_f16 a[{{[0-9]+:[0-9]+}}], v{{\[}}[[ONE]]:{{[0-9]+}}], v{{\[}}[[TWO]]:{{[0-9]+}}], 1.0
|
||||
; GFX908-COUNT-16: v_accvgpr_read_b32
|
||||
; GFX908: global_store_dwordx4
|
||||
; GFX90A-NOT: v_accvgpr_read_b32
|
||||
|
|
@ -431,6 +467,7 @@ bb:
|
|||
; NOLIT-SRCC: v_mfma_f32_32x32x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9:]+}}]
|
||||
; LIT-SRCC: v_mfma_f32_32x32x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], 0
|
||||
; GFX90A: v_mfma_f32_32x32x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], 0
|
||||
; GFX940: v_mfma_f32_32x32x1_2b_f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], 0
|
||||
; GFX908-COUNT-32: v_accvgpr_read_b32
|
||||
; GFX908: global_store_dwordx4
|
||||
; GFX90A-NOT: v_accvgpr_read_b32
|
||||
|
|
@ -450,6 +487,7 @@ bb:
|
|||
; GFX90A-DAG: v_accvgpr_mov_b32 a{{[0-9]+}}, a{{[0-9]+}}
|
||||
; GFX90A-DAG: v_accvgpr_mov_b32 a{{[0-9]+}}, a{{[0-9]+}}
|
||||
; GFX908_A: v_mfma_f32_4x4x1f32 [[RES:a\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, {{v[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
|
||||
; GFX940: v_mfma_f32_4x4x1_16b_f32 [[RES:a\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, {{v[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
|
||||
; GFX908-COUNT-4: v_accvgpr_read_b32
|
||||
; GFX908: global_store_dwordx4
|
||||
; GFX90A-NOT: v_accvgpr_read_b32
|
||||
|
|
@ -467,6 +505,7 @@ bb:
|
|||
; GFX908-COUNT-14: v_accvgpr_write_b32 a{{[0-9]+}}, 1.0
|
||||
; GFX90A-COUNT-14: v_accvgpr_mov_b32 a{{[0-9]+}}, a{{[0-9]+}}
|
||||
; GFX908_A: v_mfma_f32_16x16x1f32 a[{{[0-9]+:[0-9]+}}], {{v[0-9]+}}, {{v[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
|
||||
; GFX940: v_mfma_f32_16x16x1_4b_f32 a[{{[0-9]+:[0-9]+}}], {{v[0-9]+}}, {{v[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
|
||||
; GFX908-COUNT-16: v_accvgpr_read_b32
|
||||
; GFX908: global_store_dwordx4
|
||||
; GFX90A-NOT: v_accvgpr_read_b32
|
||||
|
|
@ -542,6 +581,7 @@ bb:
|
|||
; GFX90A-DAG: v_accvgpr_mov_b32 a{{[0-9]+}}, a{{[0-9]+}}
|
||||
; GFX90A-DAG: v_accvgpr_mov_b32 a{{[0-9]+}}, a{{[0-9]+}}
|
||||
; GFX908_A: v_mfma_f32_32x32x1f32 a[{{[0-9]+:[0-9]+}}], {{v[0-9]+}}, {{v[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
|
||||
; GFX940: v_mfma_f32_32x32x1_2b_f32 a[{{[0-9]+:[0-9]+}}], {{v[0-9]+}}, {{v[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
|
||||
; GFX908-COUNT-32: v_accvgpr_read_b32
|
||||
; GFX908: global_store_dwordx4
|
||||
; GFX90A-NOT: v_accvgpr_read_b32
|
||||
|
|
@ -555,6 +595,7 @@ bb:
|
|||
|
||||
; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32_lit_splat:
|
||||
; GFX908_A: v_mov_b32_e32 [[TMP:v[0-9]+]], 0x42f60000
|
||||
; GFX940: s_mov_b32 [[TMP:s[0-9]+]], 0x42f60000
|
||||
; GCN: v_accvgpr_write_b32 [[TTMPA:a[0-9]+]], [[TMP]]
|
||||
; GFX908: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]]
|
||||
; GFX908: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP]]
|
||||
|
|
@ -563,6 +604,7 @@ bb:
|
|||
; GFX90A: v_accvgpr_mov_b32 a{{[0-9]+}}, [[TTMPA]]
|
||||
; GFX90A: v_accvgpr_mov_b32 a{{[0-9]+}}, [[TTMPA]]
|
||||
; GFX908_A: v_mfma_f32_4x4x1f32 [[RES:a\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, {{v[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
|
||||
; GFX940: v_mfma_f32_4x4x1_16b_f32 [[RES:a\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, {{v[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
|
||||
; GFX908-COUNT-4: v_accvgpr_read_b32
|
||||
; GFX908: global_store_dwordx4
|
||||
; GFX90A-NOT: v_accvgpr_read_b32
|
||||
|
|
@ -579,16 +621,18 @@ bb:
|
|||
|
||||
; GCN-LABEL: {{^}}test_mfma_f32_4x4x1f32_lit_splat_bad_code:
|
||||
; GFX908_A: v_mov_b32_e32 [[TMP0:v[0-9]+]], 0x42f60000
|
||||
; GFX940: s_mov_b32 [[TMP0:s[0-9]+]], 0x42f60000
|
||||
; GCN: v_accvgpr_write_b32 [[AGPR:a[0-9]+]], [[TMP0]]
|
||||
; GFX90A_40-COUNT-3: v_accvgpr_mov_b32 a{{[0-9]+}}, [[AGPR]]
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP0]]
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP0]]
|
||||
; GFX908-NEXT: v_accvgpr_write_b32 a{{[0-9]+}}, [[TMP0]]
|
||||
; GFX90A-COUNT-3: v_accvgpr_mov_b32 a{{[0-9]+}}, [[AGPR]]
|
||||
; GCN: s_nop 0
|
||||
; GFX908_A: v_mfma_f32_4x4x1f32 a[{{[0-9]+:[0-9]+}}], {{v[0-9]+}}, {{v[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
|
||||
; GFX940: v_mfma_f32_4x4x1_16b_f32 a[{{[0-9]+:[0-9]+}}], {{v[0-9]+}}, {{v[0-9]+}}, a[{{[0-9]+:[0-9]+}}]
|
||||
; GFX908-COUNT-4: v_accvgpr_read_b32
|
||||
; GFX908: global_store_dwordx4 v{{[0-9]+}}, v[{{[0-9:]+}}], s[{{[0-9:]+}}]
|
||||
; GFX90A: global_store_dwordx4 v{{[0-9]+}}, a[{{[0-9:]+}}], s[{{[0-9:]+}}]
|
||||
; GFX90A_40: global_store_dwordx4 v{{[0-9]+}}, a[{{[0-9:]+}}], s[{{[0-9:]+}}]
|
||||
define amdgpu_kernel void @test_mfma_f32_4x4x1f32_lit_splat_bad_code(<4 x float> addrspace(1)* %arg) #0 {
|
||||
bb:
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
|
@ -600,19 +644,20 @@ bb:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_mfma_f32_32x32x1f32_vecarg:
|
||||
; GFX90A-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2.0
|
||||
; GFX90A-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
|
||||
; GCN-COUNT-8: global_load_dwordx4
|
||||
; GFX908-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
|
||||
; GFX90A-NOT: v_accvgpr_write
|
||||
; GFX908-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2.0
|
||||
; GFX908-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
|
||||
; GFX908: v_mfma_f32_32x32x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
|
||||
; GFX90A: v_mfma_f32_32x32x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
|
||||
; GFX908: v_accvgpr_read_b32
|
||||
; GFX908-COUNT-8: global_store_dwordx4
|
||||
; GFX90A-NOT: v_accvgpr_read_b32
|
||||
; GFX90A-COUNT-5: global_store_dwordx4 v{{[0-9:]+}}, a[{{[0-9:]+}}], s[{{[0-9:]+}}]
|
||||
; GFX90A_40-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2.0
|
||||
; GFX90A_40-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
|
||||
; GCN-COUNT-8: global_load_dwordx4
|
||||
; GFX908-COUNT-16: v_accvgpr_write_b32 a{{[0-9]+}}, v{{[0-9]+}}
|
||||
; GFX90A_40-NOT: v_accvgpr_write
|
||||
; GFX908-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2.0
|
||||
; GFX908-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
|
||||
; GFX908: v_mfma_f32_32x32x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
|
||||
; GFX90A: v_mfma_f32_32x32x1f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
|
||||
; GFX940: v_mfma_f32_32x32x1_2b_f32 a[{{[0-9]+:[0-9]+}}], [[ONE]], [[TWO]], a[{{[0-9]+:[0-9]+}}] cbsz:1 abid:2 blgp:3
|
||||
; GFX908: v_accvgpr_read_b32
|
||||
; GFX908-COUNT-8: global_store_dwordx4
|
||||
; GFX90A_40-NOT: v_accvgpr_read_b32
|
||||
; GFX90A_40-COUNT-5: global_store_dwordx4 v{{[0-9:]+}}, a[{{[0-9:]+}}], s[{{[0-9:]+}}]
|
||||
define amdgpu_kernel void @test_mfma_f32_32x32x1f32_vecarg(<32 x float> addrspace(1)* %arg) #0 {
|
||||
bb:
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
|
|
|||
Loading…
Reference in New Issue