forked from OSchip/llvm-project
LoadStoreVectorizer: Match nested adds to prove vectorization is safe
If both OpA and OpB is an add with NSW/NUW and with the same LHS operand, we can guarantee that the transformation is safe if we can prove that OpA won't overflow when IdxDiff added to the RHS of OpA. Review: https://reviews.llvm.org/D79817
This commit is contained in:
Volkan Keles
parent
736db2f710
commit
63081dc6f6
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@ -430,20 +430,78 @@ bool Vectorizer::lookThroughComplexAddresses(Value *PtrA, Value *PtrB,
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// Now we need to prove that adding IdxDiff to ValA won't overflow.
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bool Safe = false;
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auto CheckFlags = [](Instruction *I, bool Signed) {
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BinaryOperator *BinOpI = cast<BinaryOperator>(I);
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return (Signed && BinOpI->hasNoSignedWrap()) ||
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(!Signed && BinOpI->hasNoUnsignedWrap());
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};
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// First attempt: if OpB is an add with NSW/NUW, and OpB is IdxDiff added to
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// ValA, we're okay.
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if (OpB->getOpcode() == Instruction::Add &&
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isa<ConstantInt>(OpB->getOperand(1)) &&
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IdxDiff.sle(cast<ConstantInt>(OpB->getOperand(1))->getSExtValue())) {
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if (Signed)
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Safe = cast<BinaryOperator>(OpB)->hasNoSignedWrap();
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else
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Safe = cast<BinaryOperator>(OpB)->hasNoUnsignedWrap();
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IdxDiff.sle(cast<ConstantInt>(OpB->getOperand(1))->getSExtValue()) &&
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CheckFlags(OpB, Signed))
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Safe = true;
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// Second attempt: If both OpA and OpB is an add with NSW/NUW and with
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// the same LHS operand, we can guarantee that the transformation is safe
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// if we can prove that OpA won't overflow when IdxDiff added to the RHS
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// of OpA.
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// For example:
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// %tmp7 = add nsw i32 %tmp2, %v0
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// %tmp8 = sext i32 %tmp7 to i64
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// ...
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// %tmp11 = add nsw i32 %v0, 1
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// %tmp12 = add nsw i32 %tmp2, %tmp11
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// %tmp13 = sext i32 %tmp12 to i64
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//
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// Both %tmp7 and %tmp2 has the nsw flag and the first operand
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// is %tmp2. It's guaranteed that adding 1 to %tmp7 won't overflow
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// because %tmp11 adds 1 to %v0 and both %tmp11 and %tmp12 has the
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// nsw flag.
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OpA = dyn_cast<Instruction>(ValA);
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if (!Safe && OpA && OpA->getOpcode() == Instruction::Add &&
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OpB->getOpcode() == Instruction::Add &&
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OpA->getOperand(0) == OpB->getOperand(0) && CheckFlags(OpA, Signed) &&
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CheckFlags(OpB, Signed)) {
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Value *RHSA = OpA->getOperand(1);
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Value *RHSB = OpB->getOperand(1);
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Instruction *OpRHSA = dyn_cast<Instruction>(RHSA);
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Instruction *OpRHSB = dyn_cast<Instruction>(RHSB);
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// Match `x +nsw/nuw y` and `x +nsw/nuw (y +nsw/nuw IdxDiff)`.
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if (OpRHSB && OpRHSB->getOpcode() == Instruction::Add &&
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CheckFlags(OpRHSB, Signed) && isa<ConstantInt>(OpRHSB->getOperand(1))) {
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int64_t CstVal = cast<ConstantInt>(OpRHSB->getOperand(1))->getSExtValue();
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if (OpRHSB->getOperand(0) == RHSA && IdxDiff.getSExtValue() == CstVal)
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Safe = true;
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}
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// Match `x +nsw/nuw (y +nsw/nuw -Idx)` and `x +nsw/nuw (y +nsw/nuw x)`.
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if (OpRHSA && OpRHSA->getOpcode() == Instruction::Add &&
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CheckFlags(OpRHSA, Signed) && isa<ConstantInt>(OpRHSA->getOperand(1))) {
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int64_t CstVal = cast<ConstantInt>(OpRHSA->getOperand(1))->getSExtValue();
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if (OpRHSA->getOperand(0) == RHSB && IdxDiff.getSExtValue() == -CstVal)
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Safe = true;
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}
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// Match `x +nsw/nuw (y +nsw/nuw c)` and
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// `x +nsw/nuw (y +nsw/nuw (c + IdxDiff))`.
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if (OpRHSA && OpRHSB && OpRHSA->getOpcode() == Instruction::Add &&
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OpRHSB->getOpcode() == Instruction::Add && CheckFlags(OpRHSA, Signed) &&
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CheckFlags(OpRHSB, Signed) && isa<ConstantInt>(OpRHSA->getOperand(1)) &&
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isa<ConstantInt>(OpRHSB->getOperand(1))) {
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int64_t CstValA =
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cast<ConstantInt>(OpRHSA->getOperand(1))->getSExtValue();
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int64_t CstValB =
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cast<ConstantInt>(OpRHSB->getOperand(1))->getSExtValue();
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if (OpRHSA->getOperand(0) == OpRHSB->getOperand(0) &&
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IdxDiff.getSExtValue() == (CstValB - CstValA))
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Safe = true;
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}
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}
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unsigned BitWidth = ValA->getType()->getScalarSizeInBits();
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// Second attempt:
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// Third attempt:
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// If all set bits of IdxDiff or any higher order bit other than the sign bit
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// are known to be zero in ValA, we can add Diff to it while guaranteeing no
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// overflow of any sort.
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@ -0,0 +1,165 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -o - -S -load-store-vectorizer -dce %s | FileCheck %s
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; Make sure LoadStoreVectorizer vectorizes the loads below.
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; In order to prove that the vectorization is safe, it tries to
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; match nested adds and find an expression that adds a constant
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; value to an existing index and the result doesn't overflow.
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target triple = "x86_64--"
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define void @ld_v4i8_add_nsw(i32 %v0, i32 %v1, i8* %src, <4 x i8>* %dst) {
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; CHECK-LABEL: @ld_v4i8_add_nsw(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = add nsw i32 [[V0:%.*]], -1
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; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[V1:%.*]], [[TMP]]
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; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[SRC:%.*]], i64 [[TMP2]]
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[TMP3]] to <4 x i8>*
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, <4 x i8>* [[TMP0]], align 1
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; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
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; CHECK-NEXT: [[TMP82:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
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; CHECK-NEXT: [[TMP133:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
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; CHECK-NEXT: [[TMP184:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
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; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> undef, i8 [[TMP41]], i32 0
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; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP82]], i32 1
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; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP133]], i32 2
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; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP184]], i32 3
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; CHECK-NEXT: store <4 x i8> [[TMP22]], <4 x i8>* [[DST:%.*]]
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; CHECK-NEXT: ret void
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;
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bb:
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%tmp = add nsw i32 %v0, -1
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%tmp1 = add nsw i32 %v1, %tmp
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%tmp2 = sext i32 %tmp1 to i64
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%tmp3 = getelementptr inbounds i8, i8* %src, i64 %tmp2
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%tmp4 = load i8, i8* %tmp3, align 1
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%tmp5 = add nsw i32 %v1, %v0
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%tmp6 = sext i32 %tmp5 to i64
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%tmp7 = getelementptr inbounds i8, i8* %src, i64 %tmp6
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%tmp8 = load i8, i8* %tmp7, align 1
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%tmp9 = add nsw i32 %v0, 1
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%tmp10 = add nsw i32 %v1, %tmp9
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%tmp11 = sext i32 %tmp10 to i64
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%tmp12 = getelementptr inbounds i8, i8* %src, i64 %tmp11
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%tmp13 = load i8, i8* %tmp12, align 1
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%tmp14 = add nsw i32 %v0, 2
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%tmp15 = add nsw i32 %v1, %tmp14
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%tmp16 = sext i32 %tmp15 to i64
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%tmp17 = getelementptr inbounds i8, i8* %src, i64 %tmp16
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%tmp18 = load i8, i8* %tmp17, align 1
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%tmp19 = insertelement <4 x i8> undef, i8 %tmp4, i32 0
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%tmp20 = insertelement <4 x i8> %tmp19, i8 %tmp8, i32 1
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%tmp21 = insertelement <4 x i8> %tmp20, i8 %tmp13, i32 2
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%tmp22 = insertelement <4 x i8> %tmp21, i8 %tmp18, i32 3
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store <4 x i8> %tmp22, <4 x i8>* %dst
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ret void
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}
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define void @ld_v4i8_add_nuw(i32 %v0, i32 %v1, i8* %src, <4 x i8>* %dst) {
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; CHECK-LABEL: @ld_v4i8_add_nuw(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = add nuw i32 [[V0:%.*]], -1
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; CHECK-NEXT: [[TMP1:%.*]] = add nuw i32 [[V1:%.*]], [[TMP]]
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; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[SRC:%.*]], i64 [[TMP2]]
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; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8* [[TMP3]] to <4 x i8>*
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; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, <4 x i8>* [[TMP0]], align 1
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; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
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; CHECK-NEXT: [[TMP82:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
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; CHECK-NEXT: [[TMP133:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
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; CHECK-NEXT: [[TMP184:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
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; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> undef, i8 [[TMP41]], i32 0
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; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP82]], i32 1
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; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP133]], i32 2
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; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP184]], i32 3
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; CHECK-NEXT: store <4 x i8> [[TMP22]], <4 x i8>* [[DST:%.*]]
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; CHECK-NEXT: ret void
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;
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bb:
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%tmp = add nuw i32 %v0, -1
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%tmp1 = add nuw i32 %v1, %tmp
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%tmp2 = zext i32 %tmp1 to i64
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%tmp3 = getelementptr inbounds i8, i8* %src, i64 %tmp2
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%tmp4 = load i8, i8* %tmp3, align 1
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%tmp5 = add nuw i32 %v1, %v0
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%tmp6 = zext i32 %tmp5 to i64
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%tmp7 = getelementptr inbounds i8, i8* %src, i64 %tmp6
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%tmp8 = load i8, i8* %tmp7, align 1
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%tmp9 = add nuw i32 %v0, 1
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%tmp10 = add nuw i32 %v1, %tmp9
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%tmp11 = zext i32 %tmp10 to i64
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%tmp12 = getelementptr inbounds i8, i8* %src, i64 %tmp11
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%tmp13 = load i8, i8* %tmp12, align 1
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%tmp14 = add nuw i32 %v0, 2
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%tmp15 = add nuw i32 %v1, %tmp14
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%tmp16 = zext i32 %tmp15 to i64
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%tmp17 = getelementptr inbounds i8, i8* %src, i64 %tmp16
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%tmp18 = load i8, i8* %tmp17, align 1
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%tmp19 = insertelement <4 x i8> undef, i8 %tmp4, i32 0
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%tmp20 = insertelement <4 x i8> %tmp19, i8 %tmp8, i32 1
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%tmp21 = insertelement <4 x i8> %tmp20, i8 %tmp13, i32 2
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%tmp22 = insertelement <4 x i8> %tmp21, i8 %tmp18, i32 3
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store <4 x i8> %tmp22, <4 x i8>* %dst
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ret void
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}
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; Make sure we don't vectorize the loads below because the source of
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; sext instructions doesn't have the nsw flag.
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define void @ld_v4i8_add_not_safe(i32 %v0, i32 %v1, i8* %src, <4 x i8>* %dst) {
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; CHECK-LABEL: @ld_v4i8_add_not_safe(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = add nsw i32 [[V0:%.*]], -1
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; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[V1:%.*]], [[TMP]]
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; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[SRC:%.*]], i64 [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = load i8, i8* [[TMP3]], align 1
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; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[V1]], [[V0]]
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; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, i8* [[SRC]], i64 [[TMP6]]
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; CHECK-NEXT: [[TMP8:%.*]] = load i8, i8* [[TMP7]], align 1
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; CHECK-NEXT: [[TMP9:%.*]] = add nsw i32 [[V0]], 1
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; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[V1]], [[TMP9]]
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; CHECK-NEXT: [[TMP11:%.*]] = sext i32 [[TMP10]] to i64
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, i8* [[SRC]], i64 [[TMP11]]
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; CHECK-NEXT: [[TMP13:%.*]] = load i8, i8* [[TMP12]], align 1
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; CHECK-NEXT: [[TMP14:%.*]] = add nsw i32 [[V0]], 2
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; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[V1]], [[TMP14]]
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; CHECK-NEXT: [[TMP16:%.*]] = sext i32 [[TMP15]] to i64
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; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i8, i8* [[SRC]], i64 [[TMP16]]
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; CHECK-NEXT: [[TMP18:%.*]] = load i8, i8* [[TMP17]], align 1
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; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i8> undef, i8 [[TMP4]], i32 0
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; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP8]], i32 1
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; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP13]], i32 2
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; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP18]], i32 3
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; CHECK-NEXT: store <4 x i8> [[TMP22]], <4 x i8>* [[DST:%.*]]
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; CHECK-NEXT: ret void
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;
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bb:
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%tmp = add nsw i32 %v0, -1
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%tmp1 = add i32 %v1, %tmp
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%tmp2 = sext i32 %tmp1 to i64
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%tmp3 = getelementptr inbounds i8, i8* %src, i64 %tmp2
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%tmp4 = load i8, i8* %tmp3, align 1
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%tmp5 = add i32 %v1, %v0
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%tmp6 = sext i32 %tmp5 to i64
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%tmp7 = getelementptr inbounds i8, i8* %src, i64 %tmp6
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%tmp8 = load i8, i8* %tmp7, align 1
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%tmp9 = add nsw i32 %v0, 1
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%tmp10 = add i32 %v1, %tmp9
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%tmp11 = sext i32 %tmp10 to i64
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%tmp12 = getelementptr inbounds i8, i8* %src, i64 %tmp11
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%tmp13 = load i8, i8* %tmp12, align 1
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%tmp14 = add nsw i32 %v0, 2
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%tmp15 = add i32 %v1, %tmp14
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%tmp16 = sext i32 %tmp15 to i64
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%tmp17 = getelementptr inbounds i8, i8* %src, i64 %tmp16
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%tmp18 = load i8, i8* %tmp17, align 1
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%tmp19 = insertelement <4 x i8> undef, i8 %tmp4, i32 0
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%tmp20 = insertelement <4 x i8> %tmp19, i8 %tmp8, i32 1
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%tmp21 = insertelement <4 x i8> %tmp20, i8 %tmp13, i32 2
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%tmp22 = insertelement <4 x i8> %tmp21, i8 %tmp18, i32 3
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store <4 x i8> %tmp22, <4 x i8>* %dst
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ret void
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}
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