From 62f8eee0eb94f8185dad4ef8733ec51680599ce5 Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Tue, 20 Sep 2011 00:18:52 +0000
Subject: [PATCH] Thumb2 assembly parsing and encoding for UQASX/UQSAX.

llvm-svn: 140111
---
 llvm/lib/Target/ARM/ARMInstrInfo.td          |  4 +++
 llvm/test/MC/ARM/basic-thumb2-instructions.s | 28 ++++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index e325825e9e22..a30f761cef49 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -4958,6 +4958,10 @@ def : MnemonicAlias<"uaddsubx", "uasx">;
 def : MnemonicAlias<"uhaddsubx", "uhasx">;
 // UHSAX == UHSUBADDX
 def : MnemonicAlias<"uhsubaddx", "uhsax">;
+// UQASX == UQADDSUBX
+def : MnemonicAlias<"uqaddsubx", "uqasx">;
+// UQSAX == UQSUBADDX
+def : MnemonicAlias<"uqsubaddx", "uqsax">;
 
 // LDRSBT/LDRHT/LDRSHT post-index offset if optional.
 // Note that the write-back output register is a dummy operand for MC (it's
diff --git a/llvm/test/MC/ARM/basic-thumb2-instructions.s b/llvm/test/MC/ARM/basic-thumb2-instructions.s
index 71a5aaa693c7..368140360350 100644
--- a/llvm/test/MC/ARM/basic-thumb2-instructions.s
+++ b/llvm/test/MC/ARM/basic-thumb2-instructions.s
@@ -2826,3 +2826,31 @@ _func:
 @ CHECK: ite	gt                      @ encoding: [0xcc,0xbf]
 @ CHECK: uqadd16gt	r4, r7, r9      @ encoding: [0x97,0xfa,0x59,0xf4]
 @ CHECK: uqadd8le	r8, r1, r2      @ encoding: [0x81,0xfa,0x52,0xf8]
+
+
+@------------------------------------------------------------------------------
+@ UQASX/UQSAX
+@------------------------------------------------------------------------------
+        uqasx r1, r2, r3
+        uqsax r3, r4, r8
+        ite gt
+        uqasxgt r4, r7, r9
+        uqsaxle r8, r1, r2
+
+        uqaddsubx r1, r2, r3
+        uqsubaddx r3, r4, r8
+        ite gt
+        uqaddsubxgt r4, r7, r9
+        uqsubaddxle r8, r1, r2
+
+@ CHECK: uqasx	r1, r2, r3              @ encoding: [0xa2,0xfa,0x53,0xf1]
+@ CHECK: uqsax	r3, r4, r8              @ encoding: [0xe4,0xfa,0x58,0xf3]
+@ CHECK: ite	gt                      @ encoding: [0xcc,0xbf]
+@ CHECK: uqasxgt r4, r7, r9             @ encoding: [0xa7,0xfa,0x59,0xf4]
+@ CHECK: uqsaxle r8, r1, r2             @ encoding: [0xe1,0xfa,0x52,0xf8]
+
+@ CHECK: uqasx	r1, r2, r3              @ encoding: [0xa2,0xfa,0x53,0xf1]
+@ CHECK: uqsax	r3, r4, r8              @ encoding: [0xe4,0xfa,0x58,0xf3]
+@ CHECK: ite	gt                      @ encoding: [0xcc,0xbf]
+@ CHECK: uqasxgt r4, r7, r9             @ encoding: [0xa7,0xfa,0x59,0xf4]
+@ CHECK: uqsaxle r8, r1, r2             @ encoding: [0xe1,0xfa,0x52,0xf8]