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[x86][inline-asm][clang] accept 'v' constraint 

Commit on behalf of: Coby Tayree

1.'v' constraint for (x86) non-avx arch imitates the already implemented 'x' constraint, i.e. allows XMM{0-15} & YMM{0-15} depending on the apparent arch & mode (32/64).
2.for the avx512 arch it allows [X,Y,Z]MM{0-31} (mode dependent)

This patch applies the needed changes to clang
LLVM patch: https://reviews.llvm.org/D25005

Differential Revision: https://reviews.llvm.org/D25005

llvm-svn: 285688
This commit is contained in:
Michael Zuckerman 2016-11-01 13:16:44 +00:00
parent c96da1100d
commit 62f516f590
2 changed files with 32 additions and 0 deletions
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2
clang/lib/Basic/Targets.cpp
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@ -4018,6 +4018,7 @@ X86TargetInfo::validateAsmConstraint(const char *&Name,
case 'u': // Second from top of floating point stack.
case 'q': // Any register accessible as [r]l: a, b, c, and d.
case 'y': // Any MMX register.
case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
case 'x': // Any SSE register.
case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
// for intermideate k reg operations).
@ -4062,6 +4063,7 @@ bool X86TargetInfo::validateOperandSize(StringRef Constraint,
case 't':
case 'u':
return Size <= 128;
case 'v':
case 'x':
if (SSELevel >= AVX512F)
// 512-bit zmm registers can be used if target supports AVX512F.

30
clang/test/CodeGen/x86-inline-asm-v-constraint.c Normal file
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@ -0,0 +1,30 @@
// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu x86-64 -o - |opt -instnamer -S |FileCheck %s --check-prefix SSE
// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu skylake -D AVX -o -|opt -instnamer -S | FileCheck %s --check-prefixes AVX,SSE
// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu skylake-avx512 -D AVX512 -D AVX -o -|opt -instnamer -S | FileCheck %s --check-prefixes AVX512,AVX,SSE
// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu knl -D AVX -D AVX512 -o - |opt -instnamer -S | FileCheck %s --check-prefixes AVX512,AVX,SSE
typedef float __m128 __attribute__ ((vector_size (16)));
typedef float __m256 __attribute__ ((vector_size (32)));
typedef float __m512 __attribute__ ((vector_size (64)));
// SSE: call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %tmp, <4 x float> %tmp1)
__m128 testXMM(__m128 _xmm0, long _l) {
__asm__("vmovhlps %1, %2, %0" :"=v"(_xmm0) : "v"(_l), "v"(_xmm0));
return _xmm0;
}
// AVX: call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %tmp)
__m256 testYMM(__m256 _ymm0) {
#ifdef AVX
__asm__("vmovsldup %1, %0" :"=v"(_ymm0) : "v"(_ymm0));
#endif
return _ymm0;
}
// AVX512: call <16 x float> asm "vpternlogd $$0, $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %tmp, <16 x float> %tmp1)
__m512 testZMM(__m512 _zmm0, __m512 _zmm1) {
#ifdef AVX512
__asm__("vpternlogd $0, %1, %2, %0" :"=v"(_zmm0) : "v"(_zmm1), "v"(_zmm0));
#endif
return _zmm0;
}