forked from OSchip/llvm-project
Add test case for x86_64 architecture recognition in the
target.xml packet if it is included. llvm-svn: 324792
This commit is contained in:
Jason Molenda
parent
fa6113b3d7
commit
62f395e32e
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@ -0,0 +1,121 @@
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from __future__ import print_function
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import lldb
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test.decorators import *
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from gdbclientutils import *
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class TestTargetXMLArch(GDBRemoteTestBase):
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def test(self):
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"""
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Test lldb's parsing of the <architecture> tag in the target.xml register
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description packet.
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"""
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class MyResponder(MockGDBServerResponder):
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def qXferRead(self, obj, annex, offset, length):
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if annex == "target.xml":
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return """<?xml version="1.0"?>
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<target version="1.0">
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<architecture>i386:x86-64</architecture>
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<feature name="org.gnu.gdb.i386.core">
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<flags id="i386_eflags" size="4">
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<field name="CF" start="0" end="0"/>
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<field name="" start="1" end="1"/>
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<field name="PF" start="2" end="2"/>
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<field name="AF" start="4" end="4"/>
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<field name="ZF" start="6" end="6"/>
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<field name="SF" start="7" end="7"/>
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<field name="TF" start="8" end="8"/>
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<field name="IF" start="9" end="9"/>
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<field name="DF" start="10" end="10"/>
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<field name="OF" start="11" end="11"/>
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<field name="NT" start="14" end="14"/>
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<field name="RF" start="16" end="16"/>
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<field name="VM" start="17" end="17"/>
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<field name="AC" start="18" end="18"/>
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<field name="VIF" start="19" end="19"/>
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<field name="VIP" start="20" end="20"/>
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<field name="ID" start="21" end="21"/>
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</flags>
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<reg name="rax" bitsize="64" regnum="0" type="int" group="general"/>
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<reg name="rbx" bitsize="64" regnum="1" type="int" group="general"/>
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<reg name="rcx" bitsize="64" regnum="2" type="int" group="general"/>
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<reg name="rdx" bitsize="64" regnum="3" type="int" group="general"/>
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<reg name="rsi" bitsize="64" regnum="4" type="int" group="general"/>
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<reg name="rdi" bitsize="64" regnum="5" type="int" group="general"/>
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<reg name="rbp" bitsize="64" regnum="6" type="data_ptr" group="general"/>
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<reg name="rsp" bitsize="64" regnum="7" type="data_ptr" group="general"/>
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<reg name="r8" bitsize="64" regnum="8" type="int" group="general"/>
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<reg name="r9" bitsize="64" regnum="9" type="int" group="general"/>
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<reg name="r10" bitsize="64" regnum="10" type="int" group="general"/>
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<reg name="r11" bitsize="64" regnum="11" type="int" group="general"/>
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<reg name="r12" bitsize="64" regnum="12" type="int" group="general"/>
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<reg name="r13" bitsize="64" regnum="13" type="int" group="general"/>
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<reg name="r14" bitsize="64" regnum="14" type="int" group="general"/>
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<reg name="r15" bitsize="64" regnum="15" type="int" group="general"/>
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<reg name="rip" bitsize="64" regnum="16" type="code_ptr" group="general"/>
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<reg name="eflags" bitsize="32" regnum="17" type="i386_eflags" group="general"/>
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<reg name="cs" bitsize="32" regnum="18" type="int" group="general"/>
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<reg name="ss" bitsize="32" regnum="19" type="int" group="general"/>
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<reg name="ds" bitsize="32" regnum="20" type="int" group="general"/>
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<reg name="es" bitsize="32" regnum="21" type="int" group="general"/>
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<reg name="fs" bitsize="32" regnum="22" type="int" group="general"/>
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<reg name="gs" bitsize="32" regnum="23" type="int" group="general"/>
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<reg name="st0" bitsize="80" regnum="24" type="i387_ext" group="float"/>
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<reg name="st1" bitsize="80" regnum="25" type="i387_ext" group="float"/>
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<reg name="st2" bitsize="80" regnum="26" type="i387_ext" group="float"/>
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<reg name="st3" bitsize="80" regnum="27" type="i387_ext" group="float"/>
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<reg name="st4" bitsize="80" regnum="28" type="i387_ext" group="float"/>
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<reg name="st5" bitsize="80" regnum="29" type="i387_ext" group="float"/>
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<reg name="st6" bitsize="80" regnum="30" type="i387_ext" group="float"/>
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<reg name="st7" bitsize="80" regnum="31" type="i387_ext" group="float"/>
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<reg name="fctrl" bitsize="32" regnum="32" type="int" group="float"/>
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<reg name="fstat" bitsize="32" regnum="33" type="int" group="float"/>
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<reg name="ftag" bitsize="32" regnum="34" type="int" group="float"/>
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<reg name="fiseg" bitsize="32" regnum="35" type="int" group="float"/>
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<reg name="fioff" bitsize="32" regnum="36" type="int" group="float"/>
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<reg name="foseg" bitsize="32" regnum="37" type="int" group="float"/>
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<reg name="fooff" bitsize="32" regnum="38" type="int" group="float"/>
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<reg name="fop" bitsize="32" regnum="39" type="int" group="float"/>
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</feature>
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</target>""", False
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else:
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return None, False
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def qC(self):
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return "QC1"
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def haltReason(self):
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return "T05thread:00000001;06:9038d60f00700000;07:98b4062680ffffff;10:c0d7bf1b80ffffff;"
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def readRegister(self, register):
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regs = {0x0: "00b0060000610000",
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0xa: "68fe471c80ffffff",
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0xc: "60574a1c80ffffff",
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0xd: "18f3042680ffffff",
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0xe: "be8a4d7142000000",
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0xf: "50df471c80ffffff",
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0x10: "c0d7bf1b80ffffff" }
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if register in regs:
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return regs[register]
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else:
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return "0000000000000000"
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self.server.responder = MyResponder()
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interp = self.dbg.GetCommandInterpreter()
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result = lldb.SBCommandReturnObject()
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if self.TraceOn():
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interp.HandleCommand("log enable gdb-remote packets", result)
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target = self.dbg.CreateTarget('')
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self.assertEqual('', target.GetTriple())
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process = self.connect(target)
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if self.TraceOn():
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interp.HandleCommand("target list", result)
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print(result.GetOutput())
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self.assertEqual('x86_64--', target.GetTriple())
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@ -169,7 +169,7 @@ class MockGDBServerResponder:
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return "OK"
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def qSupported(self, client_supported):
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return "PacketSize=3fff;QStartNoAckMode+"
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return "qXfer:features:read+;PacketSize=3fff;QStartNoAckMode+"
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def qfThreadInfo(self):
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return "l"
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