From 62dd1b1b4f20ab0e2a6dc0980f18c7c88cee5016 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@intel.com>
Date: Fri, 17 Aug 2018 21:19:28 +0000
Subject: [PATCH] [X86] Remove detectAddSubSatPattern.

This was added very recently in r339650, but appears to be completely untested and has at least one bug in it.

llvm-svn: 340086
---
 llvm/lib/Target/X86/X86ISelLowering.cpp | 115 ------------------------
 1 file changed, 115 deletions(-)

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0aa2abc2b676..51151d5608d7 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -37211,117 +37211,6 @@ static SDValue detectPMADDUBSW(SDValue In, EVT VT, SelectionDAG &DAG,
                           PMADDBuilder);
 }
 
-/// This function detects the addition or subtraction with saturation pattern
-/// between 2  i8/i16 vectors and replace this operation with the
-/// efficient X86ISD::ADDUS/X86ISD::ADDS/X86ISD::SUBUS/X86ISD::SUBS instruction.
-static SDValue detectAddSubSatPattern(SDValue In, EVT VT, SelectionDAG &DAG,
-                                      const X86Subtarget &Subtarget,
-                                      const SDLoc &DL) {
-  if (!VT.isVector())
-    return SDValue();
-  EVT InVT = In.getValueType();
-  unsigned NumElems = VT.getVectorNumElements();
-
-  EVT ScalarVT = VT.getVectorElementType();
-  if ((ScalarVT != MVT::i8 && ScalarVT != MVT::i16) ||
-      InVT.getSizeInBits() % 128 != 0 || !isPowerOf2_32(NumElems))
-    return SDValue();
-
-  // InScalarVT is the intermediate type in AddSubSat pattern
-  // and it should be greater than the output type.
-  EVT InScalarVT = InVT.getVectorElementType();
-  if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
-    return SDValue();
-
-  if (!Subtarget.hasSSE2())
-    return SDValue();
-
-  // Detect the following pattern:
-  // %2 = zext <16 x i8> %0 to <16 x i16>
-  // %3 = zext <16 x i8> %1 to <16 x i16>
-  // %4 = add nuw nsw <16 x i16> %3, %2
-  // %5 = icmp ult <16 x i16> %4, <16 x i16> (vector of max InScalarVT values)
-  // %6 = select <16 x i1> %5, <16 x i16> (vector of max InScalarVT values)
-  // %7 = trunc <16 x i16> %6 to <16 x i8>
-
-  // Detect a Sat Pattern
-  bool Signed = true;
-  SDValue Sat = detectSSatPattern(In, VT, false);
-  if (!Sat) {
-    Sat = detectUSatPattern(In, VT, DAG, DL);
-    Signed = false;
-  }
-  if (!Sat)
-    return SDValue();
-  if (Sat.getOpcode() != ISD::ADD && Sat.getOpcode() != ISD::SUB)
-    return SDValue();
-
-  unsigned Opcode = Sat.getOpcode() == ISD::ADD ? Signed ? X86ISD::ADDS
-                                                         : X86ISD::ADDUS
-                                                : Signed ? X86ISD::SUBS
-                                                         : X86ISD::SUBUS;
-
-  // Get addition elements.
-  SDValue LHS = Sat.getOperand(0);
-  SDValue RHS = Sat.getOperand(1);
-
-  // Don't combine if both operands are constant.
-  if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
-      ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
-    return SDValue();
-
-  // Check if Op is a result of type promotion.
-  auto IsExtended = [=, &DAG](SDValue Op) {
-    unsigned Opcode = Op.getOpcode();
-    unsigned EltSize = ScalarVT.getSizeInBits();
-    unsigned ExtEltSize = InScalarVT.getSizeInBits();
-    unsigned ExtPartSize = ExtEltSize - EltSize;
-
-    // Extension of non-constant operand.
-    if (Opcode == ISD::ZERO_EXTEND || Opcode == ISD::SIGN_EXTEND) {
-      if (Signed)
-        return DAG.ComputeNumSignBits(Op) > ExtPartSize;
-      else {
-        APInt HighBitsMask = APInt::getHighBitsSet(ExtEltSize, ExtPartSize);
-        return DAG.MaskedValueIsZero(Op, HighBitsMask);
-      }
-    } else if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
-      // Build vector of constant nodes. Each of them needs to be a correct
-      // extension from a constant of ScalarVT type.
-      unsigned NumOperands = Op.getNumOperands();
-      for (unsigned i = 0; i < NumOperands; ++i) {
-        SDValue Elem = Op.getOperand(i);
-        if (Elem.isUndef())
-          return false;
-        APInt Elt = cast<ConstantSDNode>(Elem)->getAPIntValue();
-        if ((Signed && !Elt.isSignedIntN(EltSize)) ||
-            (!Signed && !Elt.isIntN(EltSize)))
-          return false;
-      }
-      return true;
-    }
-    return false;
-  };
-
-  // Either both operands are extended or one of them is extended
-  // and another one is a vector of constants.
-  if (!IsExtended(LHS) || !IsExtended(RHS))
-    return SDValue();
-
-  // Truncate extended nodes to result type.
-  LHS = DAG.getNode(ISD::TRUNCATE, DL, VT, LHS);
-  RHS = DAG.getNode(ISD::TRUNCATE, DL, VT, RHS);
- 
-  // The pattern is detected, emit ADDS/ADDUS/SUBS/SUBUS instruction.
-  auto AddSubSatBuilder = [Opcode](SelectionDAG &DAG, const SDLoc &DL,
-                                   ArrayRef<SDValue> Ops) {
-    EVT VT = Ops[0].getValueType();
-    return DAG.getNode(Opcode, DL, VT, Ops);
-  };
-  return SplitOpsAndApply(DAG, Subtarget, DL, VT, { LHS, RHS },
-                          AddSubSatBuilder);
-}
-
 static SDValue combineTruncate(SDNode *N, SelectionDAG &DAG,
                                const X86Subtarget &Subtarget) {
   EVT VT = N->getValueType(0);
@@ -37340,10 +37229,6 @@ static SDValue combineTruncate(SDNode *N, SelectionDAG &DAG,
   if (SDValue PMAdd = detectPMADDUBSW(Src, VT, DAG, Subtarget, DL))
     return PMAdd;
 
-  // Try to detect addition or subtraction with saturation.
-  if (SDValue AddSubSat = detectAddSubSatPattern(Src, VT, DAG, Subtarget, DL))
-    return AddSubSat;
-
   // Try to combine truncation with signed/unsigned saturation.
   if (SDValue Val = combineTruncateWithSat(Src, VT, DL, DAG, Subtarget))
     return Val;