forked from OSchip/llvm-project
- Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit
immediate in small code model. The JIT cannot ensure GV's are placed in the lower 4G. - Some preliminary support for large code model. llvm-svn: 32215
This commit is contained in:
Evan Cheng
parent
830f224bf5
commit
62cdc3f011
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@ -59,12 +59,12 @@ namespace {
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void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
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void emitPCRelativeValue(intptr_t Address);
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void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
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void emitGlobalAddressForPtr(GlobalValue *GV, bool isPCRelative,
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void emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
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int Disp = 0, unsigned PCAdj = 0);
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void emitExternalSymbolAddress(const char *ES, bool isPCRelative);
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void emitPCRelativeConstPoolAddress(unsigned CPI, int Disp = 0,
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unsigned PCAdj = 0);
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void emitPCRelativeJumpTableAddress(unsigned JTI, unsigned PCAdj = 0);
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void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
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void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
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unsigned PCAdj = 0);
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void emitJumpTableAddress(unsigned JTI, unsigned Reloc, unsigned PCAdj = 0);
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void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
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unsigned PCAdj = 0);
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@ -144,41 +144,45 @@ void Emitter::emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub) {
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/// emitGlobalAddress - Emit the specified address to the code stream assuming
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/// this is part of a "take the address of a global" instruction.
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///
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void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, bool isPCRelative,
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void Emitter::emitGlobalAddressForPtr(GlobalValue *GV, unsigned Reloc,
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int Disp /* = 0 */,
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unsigned PCAdj /* = 0 */) {
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unsigned rt = isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
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MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), rt,
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MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
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GV, PCAdj));
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if (Reloc == X86::reloc_absolute_dword)
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MCE.emitWordLE(0);
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MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
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}
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/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitExternalSymbolAddress(const char *ES, bool isPCRelative) {
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void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
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MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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isPCRelative ? X86::reloc_pcrel_word : X86::reloc_absolute_word, ES));
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Reloc, ES));
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if (Reloc == X86::reloc_absolute_dword)
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MCE.emitWordLE(0);
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MCE.emitWordLE(0);
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}
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/// emitPCRelativeConstPoolAddress - Arrange for the address of an constant pool
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/// emitConstPoolAddress - Arrange for the address of an constant pool
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/// to be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitPCRelativeConstPoolAddress(unsigned CPI, int Disp /* = 0 */,
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unsigned PCAdj /* = 0 */) {
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void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
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int Disp /* = 0 */,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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X86::reloc_pcrel_word, CPI, PCAdj));
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Reloc, CPI, PCAdj));
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MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
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}
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/// emitPCRelativeJumpTableAddress - Arrange for the address of a jump table to
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/// emitJumpTableAddress - Arrange for the address of a jump table to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitPCRelativeJumpTableAddress(unsigned JTI,
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unsigned PCAdj /* = 0 */) {
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void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
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X86::reloc_pcrel_word, JTI, PCAdj));
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Reloc, JTI, PCAdj));
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MCE.emitWordLE(0); // The relocated value will be added to the displacement
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}
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@ -291,15 +295,17 @@ void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
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// But it's probably not beneficial.
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// 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
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// 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
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emitGlobalAddressForPtr(RelocOp->getGlobal(), Is64BitMode,
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unsigned rt= Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
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emitGlobalAddressForPtr(RelocOp->getGlobal(), rt,
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RelocOp->getOffset(), PCAdj);
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} else if (RelocOp->isConstantPoolIndex()) {
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// Must be in 64-bit mode.
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emitPCRelativeConstPoolAddress(RelocOp->getConstantPoolIndex(),
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RelocOp->getOffset(), PCAdj);
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emitConstPoolAddress(RelocOp->getConstantPoolIndex(), X86::reloc_pcrel_word,
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RelocOp->getOffset(), PCAdj);
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} else if (RelocOp->isJumpTableIndex()) {
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// Must be in 64-bit mode.
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emitPCRelativeJumpTableAddress(RelocOp->getJumpTableIndex(), PCAdj);
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emitJumpTableAddress(RelocOp->getJumpTableIndex(), X86::reloc_pcrel_word,
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PCAdj);
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} else {
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assert(0 && "Unknown value to relocate!");
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}
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@ -417,8 +423,8 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
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}
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}
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static unsigned sizeOfImm(const TargetInstrDescriptor &Desc) {
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switch (Desc.TSFlags & X86II::ImmMask) {
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static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
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switch (Desc->TSFlags & X86II::ImmMask) {
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case X86II::Imm8: return 1;
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case X86II::Imm16: return 2;
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case X86II::Imm32: return 4;
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@ -459,19 +465,19 @@ inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
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/// size, and 3) use of X86-64 extended registers.
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unsigned Emitter::determineREX(const MachineInstr &MI) {
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unsigned REX = 0;
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDescriptor &Desc = II->get(Opcode);
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const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
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unsigned Opcode = Desc->Opcode;
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// Pseudo instructions do not need REX prefix byte.
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if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
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if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
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return 0;
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if (Desc.TSFlags & X86II::REX_W)
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if (Desc->TSFlags & X86II::REX_W)
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REX |= 1 << 3;
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unsigned NumOps = II->getNumOperands(Opcode);
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unsigned NumOps = Desc->numOperands;
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if (NumOps) {
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bool isTwoAddr = NumOps > 1 &&
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II->getOperandConstraint(Opcode, 1, TOI::TIED_TO) != -1;
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Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
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// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
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bool isTrunc8 = isX86_64TruncToByte(Opcode);
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@ -489,7 +495,7 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
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}
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}
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switch (Desc.TSFlags & X86II::FormMask) {
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switch (Desc->TSFlags & X86II::FormMask) {
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case X86II::MRMInitReg:
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if (isX86_64ExtendedReg(MI.getOperand(0)))
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REX |= (1 << 0) | (1 << 2);
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@ -559,20 +565,20 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
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void Emitter::emitInstruction(const MachineInstr &MI) {
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NumEmitted++; // Keep track of the # of mi's emitted
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unsigned Opcode = MI.getOpcode();
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const TargetInstrDescriptor &Desc = II->get(Opcode);
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const TargetInstrDescriptor *Desc = MI.getInstrDescriptor();
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unsigned Opcode = Desc->Opcode;
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// Emit the repeat opcode prefix as needed.
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if ((Desc.TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
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if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
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// Emit the operand size opcode prefix as needed.
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if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);
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if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
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// Emit the address size opcode prefix as needed.
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if (Desc.TSFlags & X86II::AdSize) MCE.emitByte(0x67);
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if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
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bool Need0FPrefix = false;
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switch (Desc.TSFlags & X86II::Op0Mask) {
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switch (Desc->TSFlags & X86II::Op0Mask) {
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case X86II::TB:
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Need0FPrefix = true; // Two-byte opcode prefix
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break;
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@ -588,7 +594,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
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case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
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case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
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MCE.emitByte(0xD8+
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(((Desc.TSFlags & X86II::Op0Mask)-X86II::D8)
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(((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
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>> X86II::Op0Shift));
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break; // Two-byte opcode prefix
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default: assert(0 && "Invalid prefix!");
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@ -607,14 +613,13 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
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MCE.emitByte(0x0F);
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// If this is a two-address instruction, skip one of the register operands.
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unsigned NumOps = II->getNumOperands(Opcode);
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unsigned NumOps = Desc->numOperands;
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unsigned CurOp = 0;
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if (NumOps > 1 &&
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II->getOperandConstraint(Opcode, 1, TOI::TIED_TO) != -1)
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if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
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CurOp++;
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unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
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switch (Desc.TSFlags & X86II::FormMask) {
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unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
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switch (Desc->TSFlags & X86II::FormMask) {
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default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
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case X86II::Pseudo:
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#ifndef NDEBUG
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@ -651,7 +656,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
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Opcode == X86::TAILJMPr || Opcode == X86::TAILJMPm;
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emitGlobalAddressForCall(MO.getGlobal(), !isTailCall);
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} else if (MO.isExternalSymbol()) {
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emitExternalSymbolAddress(MO.getSymbolName(), true);
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emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
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} else if (MO.isImmediate()) {
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emitConstant(MO.getImm(), sizeOfImm(Desc));
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} else {
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@ -665,20 +670,22 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
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if (CurOp != NumOps) {
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const MachineOperand &MO1 = MI.getOperand(CurOp++);
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if (MO1.isGlobalAddress()) {
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assert(sizeOfImm(Desc) == TD->getPointerSize() &&
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"Don't know how to emit non-pointer values!");
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emitGlobalAddressForPtr(MO1.getGlobal(), Is64BitMode, MO1.getOffset());
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} else if (MO1.isExternalSymbol()) {
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assert(sizeOfImm(Desc) == TD->getPointerSize() &&
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"Don't know how to emit non-pointer values!");
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emitExternalSymbolAddress(MO1.getSymbolName(), false);
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} else if (MO1.isJumpTableIndex()) {
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assert(sizeOfImm(Desc) == TD->getPointerSize() &&
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"Don't know how to emit non-pointer values!");
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emitConstant(MCE.getJumpTableEntryAddress(MO1.getJumpTableIndex()), 4);
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} else {
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emitConstant(MO1.getImm(), sizeOfImm(Desc));
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unsigned Size = sizeOfImm(Desc);
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if (MO1.isImmediate())
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emitConstant(MO1.getImm(), Size);
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else {
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unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
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// FIXME
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if (Opcode == X86::MOV64ri)
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rt = X86::reloc_absolute_dword;
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if (MO1.isGlobalAddress())
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emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
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else if (MO1.isExternalSymbol())
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emitExternalSymbolAddress(MO1.getSymbolName(), rt);
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else if (MO1.isConstantPoolIndex())
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emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
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else if (MO1.isJumpTableIndex())
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emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
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}
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}
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break;
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@ -728,10 +735,28 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
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case X86II::MRM6r: case X86II::MRM7r:
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MCE.emitByte(BaseOpcode);
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emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
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(Desc.TSFlags & X86II::FormMask)-X86II::MRM0r);
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(Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
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if (CurOp != NumOps && MI.getOperand(CurOp).isImmediate())
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emitConstant(MI.getOperand(CurOp++).getImm(), sizeOfImm(Desc));
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if (CurOp != NumOps) {
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const MachineOperand &MO1 = MI.getOperand(CurOp++);
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unsigned Size = sizeOfImm(Desc);
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if (MO1.isImmediate())
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emitConstant(MO1.getImm(), Size);
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else {
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unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
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// FIXME
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if (Opcode == X86::MOV64ri32)
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rt = X86::reloc_absolute_word;
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if (MO1.isGlobalAddress())
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emitGlobalAddressForPtr(MO1.getGlobal(), rt, MO1.getOffset());
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else if (MO1.isExternalSymbol())
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emitExternalSymbolAddress(MO1.getSymbolName(), rt);
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else if (MO1.isConstantPoolIndex())
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emitConstPoolAddress(MO1.getConstantPoolIndex(), rt);
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else if (MO1.isJumpTableIndex())
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emitJumpTableAddress(MO1.getJumpTableIndex(), rt);
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}
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}
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break;
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case X86II::MRM0m: case X86II::MRM1m:
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@ -742,20 +767,26 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
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(MI.getOperand(CurOp+4).isImmediate() ? sizeOfImm(Desc) : 4) : 0;
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MCE.emitByte(BaseOpcode);
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emitMemModRMByte(MI, CurOp, (Desc.TSFlags & X86II::FormMask)-X86II::MRM0m,
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emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
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PCAdj);
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CurOp += 4;
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if (CurOp != NumOps) {
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const MachineOperand &MO = MI.getOperand(CurOp++);
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unsigned Size = sizeOfImm(Desc);
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if (MO.isImmediate())
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emitConstant(MO.getImm(), sizeOfImm(Desc));
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else if (MO.isGlobalAddress())
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emitGlobalAddressForPtr(MO.getGlobal(), Is64BitMode, MO.getOffset());
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else if (MO.isJumpTableIndex())
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emitConstant(MCE.getJumpTableEntryAddress(MO.getJumpTableIndex()), 4);
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else
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assert(0 && "Unknown operand!");
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emitConstant(MO.getImm(), Size);
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else {
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unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_absolute_word;
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if (MO.isGlobalAddress())
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emitGlobalAddressForPtr(MO.getGlobal(), rt, MO.getOffset());
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else if (MO.isExternalSymbol())
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emitExternalSymbolAddress(MO.getSymbolName(), rt);
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else if (MO.isConstantPoolIndex())
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emitConstPoolAddress(MO.getConstantPoolIndex(), rt);
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else if (MO.isJumpTableIndex())
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emitJumpTableAddress(MO.getJumpTableIndex(), rt);
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}
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}
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break;
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}
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@ -769,6 +800,6 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
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break;
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}
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assert((Desc.Flags & M_VARIABLE_OPS) != 0 ||
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assert((Desc->Flags & M_VARIABLE_OPS) != 0 ||
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CurOp == NumOps && "Unknown encoding!");
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}
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@ -590,11 +590,10 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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break;
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}
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case X86ISD::Wrapper:
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case X86ISD::WrapperRIP: {
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bool isRIP = N.getOpcode() == X86ISD::WrapperRIP;
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case X86ISD::Wrapper: {
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bool is64Bit = Subtarget->is64Bit();
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// Under X86-64 non-small code model, GV (and friends) are 64-bits.
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if (!isRIP && Subtarget->is64Bit() && TM.getCodeModel() != CodeModel::Small)
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if (is64Bit && TM.getCodeModel() != CodeModel::Small)
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break;
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// If value is available in a register both base and index components have
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@ -603,7 +602,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
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// For X86-64 PIC code, only allow GV / CP + displacement so we can use
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// RIP relative addressing mode.
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if (isRIP &&
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if (is64Bit &&
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(AM.Base.Reg.Val || AM.Scale > 1 || AM.IndexReg.Val ||
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AM.BaseType == X86ISelAddressMode::FrameIndexBase))
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break;
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@ -613,7 +612,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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AM.CP = CP->getConstVal();
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AM.Align = CP->getAlignment();
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AM.Disp += CP->getOffset();
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AM.isRIPRel = isRIP;
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AM.isRIPRel = is64Bit;
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return false;
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}
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} else if (GlobalAddressSDNode *G =
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@ -621,10 +620,10 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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if (AM.GV == 0) {
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AM.GV = G->getGlobal();
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AM.Disp += G->getOffset();
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AM.isRIPRel = isRIP;
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AM.isRIPRel = is64Bit;
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return false;
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}
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} else if (isRoot && isRIP) {
|
||||
} else if (isRoot && is64Bit) {
|
||||
if (ExternalSymbolSDNode *S =
|
||||
dyn_cast<ExternalSymbolSDNode>(N.getOperand(0))) {
|
||||
AM.ES = S->getSymbol();
|
||||
|
|
@ -997,8 +996,7 @@ SDNode *X86DAGToDAGISel::Select(SDOperand N) {
|
|||
SDOperand N0 = N.getOperand(0);
|
||||
SDOperand N1 = N.getOperand(1);
|
||||
if (N.Val->getValueType(0) == PtrVT &&
|
||||
(N0.getOpcode() == X86ISD::Wrapper
|
||||
|| N0.getOpcode() == X86ISD::WrapperRIP) &&
|
||||
N0.getOpcode() == X86ISD::Wrapper &&
|
||||
N1.getOpcode() == ISD::Constant) {
|
||||
unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
|
||||
SDOperand C(0, 0);
|
||||
|
|
|
|||
|
|
@ -3832,14 +3832,7 @@ X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
|
|||
SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
|
||||
getPointerTy(),
|
||||
CP->getAlignment());
|
||||
// Use X86ISD::WrapperRIP if we are in X86-64 small / medium PIC mode.
|
||||
TargetMachine &tm = getTargetMachine();
|
||||
unsigned WrapperOpcode = (Subtarget->is64Bit() &&
|
||||
(tm.getCodeModel() == CodeModel::Small ||
|
||||
tm.getCodeModel() == CodeModel::Medium) &&
|
||||
tm.getRelocationModel() == Reloc::PIC_)
|
||||
? X86ISD::WrapperRIP : X86ISD::Wrapper;
|
||||
Result = DAG.getNode(WrapperOpcode, getPointerTy(), Result);
|
||||
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
|
||||
if (Subtarget->isTargetDarwin()) {
|
||||
// With PIC, the address is actually $g + Offset.
|
||||
if (!Subtarget->is64Bit() &&
|
||||
|
|
@ -3855,14 +3848,7 @@ SDOperand
|
|||
X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
|
||||
GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
||||
SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
|
||||
// Use X86ISD::WrapperRIP if we are in X86-64 small / medium PIC mode.
|
||||
TargetMachine &tm = getTargetMachine();
|
||||
unsigned WrapperOpcode = (Subtarget->is64Bit() &&
|
||||
(tm.getCodeModel() == CodeModel::Small ||
|
||||
tm.getCodeModel() == CodeModel::Medium) &&
|
||||
tm.getRelocationModel() == Reloc::PIC_)
|
||||
? X86ISD::WrapperRIP : X86ISD::Wrapper;
|
||||
Result = DAG.getNode(WrapperOpcode, getPointerTy(), Result);
|
||||
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
|
||||
if (Subtarget->isTargetDarwin()) {
|
||||
// With PIC, the address is actually $g + Offset.
|
||||
if (!Subtarget->is64Bit() &&
|
||||
|
|
@ -3889,14 +3875,7 @@ SDOperand
|
|||
X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
|
||||
const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
|
||||
SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
|
||||
// Use X86ISD::WrapperRIP if we are in X86-64 small / medium PIC mode.
|
||||
TargetMachine &tm = getTargetMachine();
|
||||
unsigned WrapperOpcode = (Subtarget->is64Bit() &&
|
||||
(tm.getCodeModel() == CodeModel::Small ||
|
||||
tm.getCodeModel() == CodeModel::Medium) &&
|
||||
tm.getRelocationModel() == Reloc::PIC_)
|
||||
? X86ISD::WrapperRIP : X86ISD::Wrapper;
|
||||
Result = DAG.getNode(WrapperOpcode, getPointerTy(), Result);
|
||||
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
|
||||
if (Subtarget->isTargetDarwin()) {
|
||||
// With PIC, the address is actually $g + Offset.
|
||||
if (!Subtarget->is64Bit() &&
|
||||
|
|
@ -4264,14 +4243,7 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
|
|||
SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
|
||||
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
|
||||
SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
|
||||
// Use X86ISD::WrapperRIP if we are in X86-64 small / medium PIC mode.
|
||||
TargetMachine &tm = getTargetMachine();
|
||||
unsigned WrapperOpcode = (Subtarget->is64Bit() &&
|
||||
(tm.getCodeModel() == CodeModel::Small ||
|
||||
tm.getCodeModel() == CodeModel::Medium) &&
|
||||
tm.getRelocationModel() == Reloc::PIC_)
|
||||
? X86ISD::WrapperRIP : X86ISD::Wrapper;
|
||||
Result = DAG.getNode(WrapperOpcode, getPointerTy(), Result);
|
||||
Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
|
||||
if (Subtarget->isTargetDarwin()) {
|
||||
// With PIC, the address is actually $g + Offset.
|
||||
if (!Subtarget->is64Bit() &&
|
||||
|
|
@ -5005,7 +4977,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|||
case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA";
|
||||
case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
|
||||
case X86ISD::Wrapper: return "X86ISD::Wrapper";
|
||||
case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
|
||||
case X86ISD::S2VEC: return "X86ISD::S2VEC";
|
||||
case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
|
||||
case X86ISD::PINSRW: return "X86ISD::PINSRW";
|
||||
|
|
@ -5249,7 +5220,7 @@ static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
|
|||
/// node is a GlobalAddress + an offset.
|
||||
static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
|
||||
unsigned Opc = N->getOpcode();
|
||||
if (Opc == X86ISD::Wrapper || Opc == X86ISD::WrapperRIP) {
|
||||
if (Opc == X86ISD::Wrapper) {
|
||||
if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
|
||||
GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
|
||||
return true;
|
||||
|
|
|
|||
|
|
@ -277,8 +277,8 @@ public:
|
|||
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
|
||||
// specified opcode number.
|
||||
//
|
||||
unsigned char getBaseOpcodeFor(unsigned Opcode) const {
|
||||
return get(Opcode).TSFlags >> X86II::OpcodeShift;
|
||||
unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
|
||||
return TID->TSFlags >> X86II::OpcodeShift;
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ def lea64_32mem : Operand<i32> {
|
|||
// Complex Pattern Definitions...
|
||||
//
|
||||
def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
|
||||
[add, mul, shl, or, frameindex, X86WrapperRIP],
|
||||
[add, mul, shl, or, frameindex, X86Wrapper],
|
||||
[]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -1022,15 +1022,6 @@ def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (ops GR64:$dst, i64i32imm:$src),
|
|||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
|
||||
def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
|
||||
(MOV64ri32 tconstpool :$dst)>, Requires<[SmallCode]>;
|
||||
def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
|
||||
(MOV64ri32 tjumptable :$dst)>, Requires<[SmallCode]>;
|
||||
def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
|
||||
(MOV64ri32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
|
||||
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
|
||||
(MOV64ri32 texternalsym:$dst)>, Requires<[SmallCode]>;
|
||||
|
||||
def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
|
||||
(MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
|
||||
def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
|
||||
|
|
@ -1040,10 +1031,12 @@ def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
|
|||
def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
|
||||
(MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
|
||||
|
||||
/*
|
||||
def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
|
||||
(MOV64mi32 addr:$dst, tglobaladdr:$src)>, Requires<[SmallCode]>;
|
||||
def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
|
||||
(MOV64mi32 addr:$dst, texternalsym:$src)>, Requires<[SmallCode]>;
|
||||
*/
|
||||
|
||||
// Calls
|
||||
// Direct PC relative function call for small code model. 32-bit displacement
|
||||
|
|
|
|||
|
|
@ -323,6 +323,9 @@ void X86JITInfo::relocate(void *Function, MachineRelocation *MR,
|
|||
// in memory.
|
||||
*((unsigned*)RelocPos) += (unsigned)ResultPtr;
|
||||
break;
|
||||
case X86::reloc_absolute_dword:
|
||||
*((intptr_t*)RelocPos) += ResultPtr;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,9 +23,10 @@ namespace llvm {
|
|||
// the value already in memory, after we adjust it for where the PC is.
|
||||
reloc_pcrel_word = 0,
|
||||
|
||||
// reloc_absolute_word - Absolute relocation, just add the relocated value
|
||||
// to the value already in memory.
|
||||
reloc_absolute_word = 1
|
||||
// reloc_absolute_word, reloc_absolute_dword - Absolute relocation, just
|
||||
// add the relocated value to the value already in memory.
|
||||
reloc_absolute_word = 1,
|
||||
reloc_absolute_dword = 2
|
||||
};
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue