forked from OSchip/llvm-project
[GlobalISel][AArch64] Select ADDXri.
We're now able to select ADDWri thanks to the new complex pattern support. Extend that to ADDXri. llvm-svn: 297874
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@ -22,6 +22,7 @@
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class LLT;
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def s32 : LLT;
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def s64 : LLT;
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// Defines a matcher for complex operands. This is analogous to ComplexPattern
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// from SelectionDAG.
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@ -693,6 +693,10 @@ def gi_addsub_shifted_imm32 :
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GIComplexOperandMatcher<s32, (ops i32imm, i32imm), "selectArithImmed">,
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GIComplexPatternEquiv<addsub_shifted_imm32>;
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def gi_addsub_shifted_imm64 :
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GIComplexOperandMatcher<s64, (ops i32imm, i32imm), "selectArithImmed">,
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GIComplexPatternEquiv<addsub_shifted_imm64>;
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class neg_addsub_shifted_imm<ValueType Ty>
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: Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
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let PrintMethod = "printAddSubImm";
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@ -7,6 +7,8 @@
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define void @add_s64_gpr() { ret void }
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define void @add_imm_s32_gpr() { ret void }
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define void @add_imm_s64_gpr() { ret void }
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define void @add_imm_s32_gpr_bb() { ret void }
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define void @sub_s32_gpr() { ret void }
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@ -139,6 +141,33 @@ body: |
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%2(s32) = G_ADD %0, %1
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...
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---
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# CHECK-LABEL: name: add_imm_s64_gpr
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name: add_imm_s64_gpr
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legalized: true
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regBankSelected: true
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# CHECK: registers:
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# CHECK-NEXT: - { id: 0, class: gpr64sp }
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# CHECK-NEXT: - { id: 1, class: gpr64 }
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# CHECK-NEXT: - { id: 2, class: gpr64sp }
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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# CHECK: body:
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# CHECK: %0 = COPY %x0
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# CHECK: %2 = ADDXri %0, 1, 0
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body: |
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bb.0:
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liveins: %x0, %w1
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%0(s64) = COPY %x0
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%1(s64) = G_CONSTANT 1
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%2(s64) = G_ADD %0, %1
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...
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---
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# CHECK-LABEL: name: add_imm_s32_gpr_bb
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name: add_imm_s32_gpr_bb
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