forked from OSchip/llvm-project
[AMDGPU][NFC] Rename opsel/opsel_hi/neg_lo/neg_hi with suffix 0
These parameters set a default value of 0, so I believe they should include a 0 suffix. This allows for versions which do not set a default value in future. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D93187
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@ -1136,10 +1136,10 @@ def src0_sel : NamedOperandU32<"SDWASrc0Sel", NamedMatchClass<"SDWASrc0Sel">>;
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def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>;
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def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>;
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def op_sel : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>;
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def op_sel_hi : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>;
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def neg_lo : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>;
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def neg_hi : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>;
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def op_sel0 : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>;
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def op_sel_hi0 : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>;
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def neg_lo0 : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>;
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def neg_hi0 : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>;
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def blgp : NamedOperandU32<"BLGP", NamedMatchClass<"BLGP">>;
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def cbsz : NamedOperandU32<"CBSZ", NamedMatchClass<"CBSZ">>;
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@ -1677,25 +1677,25 @@ class getInsVOP3P <RegisterOperand Src0RC, RegisterOperand Src1RC,
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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clampmod0:$clamp,
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op_sel:$op_sel, op_sel_hi:$op_sel_hi,
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neg_lo:$neg_lo, neg_hi:$neg_hi),
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op_sel0:$op_sel, op_sel_hi0:$op_sel_hi,
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neg_lo0:$neg_lo, neg_hi0:$neg_hi),
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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op_sel:$op_sel, op_sel_hi:$op_sel_hi,
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neg_lo:$neg_lo, neg_hi:$neg_hi)),
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op_sel0:$op_sel, op_sel_hi0:$op_sel_hi,
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neg_lo0:$neg_lo, neg_hi0:$neg_hi)),
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// else NumSrcArgs == 3
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!if (HasClamp,
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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Src2Mod:$src2_modifiers, Src2RC:$src2,
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clampmod0:$clamp,
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op_sel:$op_sel, op_sel_hi:$op_sel_hi,
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neg_lo:$neg_lo, neg_hi:$neg_hi),
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op_sel0:$op_sel, op_sel_hi0:$op_sel_hi,
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neg_lo0:$neg_lo, neg_hi0:$neg_hi),
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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Src2Mod:$src2_modifiers, Src2RC:$src2,
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op_sel:$op_sel, op_sel_hi:$op_sel_hi,
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neg_lo:$neg_lo, neg_hi:$neg_hi))
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op_sel0:$op_sel, op_sel_hi0:$op_sel_hi,
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neg_lo0:$neg_lo, neg_hi0:$neg_hi))
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);
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}
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@ -1712,21 +1712,21 @@ class getInsVOP3OpSel <RegisterOperand Src0RC,
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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clampmod0:$clamp,
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op_sel:$op_sel),
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op_sel0:$op_sel),
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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op_sel:$op_sel)),
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op_sel0:$op_sel)),
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// else NumSrcArgs == 3
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!if (HasClamp,
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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Src2Mod:$src2_modifiers, Src2RC:$src2,
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clampmod0:$clamp,
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op_sel:$op_sel),
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op_sel0:$op_sel),
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(ins Src0Mod:$src0_modifiers, Src0RC:$src0,
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Src1Mod:$src1_modifiers, Src1RC:$src1,
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Src2Mod:$src2_modifiers, Src2RC:$src2,
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op_sel:$op_sel))
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op_sel0:$op_sel))
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);
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}
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@ -694,7 +694,7 @@ def VOP3_PERMLANE_Profile : VOP3_Profile<VOPProfile <[i32, i32, i32, i32]>, VOP3
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let InsVOP3OpSel = (ins IntOpSelMods:$src0_modifiers, VRegSrc_32:$src0,
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IntOpSelMods:$src1_modifiers, SCSrc_b32:$src1,
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IntOpSelMods:$src2_modifiers, SCSrc_b32:$src2,
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VGPR_32:$vdst_in, op_sel:$op_sel);
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VGPR_32:$vdst_in, op_sel0:$op_sel);
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let HasClamp = 0;
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let HasOMod = 0;
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}
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@ -39,7 +39,7 @@ class VOP3_VOP3PInst<string OpName, VOPProfile P, bit UseTiedOutput = 0,
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// class constraints.
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!if(UseTiedOutput, (ins clampmod:$clamp, VGPR_32:$vdst_in),
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(ins clampmod0:$clamp))),
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(ins op_sel:$op_sel, op_sel_hi:$op_sel_hi));
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(ins op_sel0:$op_sel, op_sel_hi0:$op_sel_hi));
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let Constraints = !if(UseTiedOutput, "$vdst = $vdst_in", "");
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let DisableEncoding = !if(UseTiedOutput, "$vdst_in", "");
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