forked from OSchip/llvm-project
Added clamp i64 to i16 global isel pattern.
This commit is contained in:
Thomas Symalla
parent
e7f9a83499
commit
62af0305b7
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@ -468,6 +468,14 @@ m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
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TargetOpcode::G_INSERT_VECTOR_ELT>(Src0, Src1, Src2);
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}
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template <typename Src0Ty, typename Src1Ty, typename Src2Ty>
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inline TernaryOp_match<Src0Ty, Src1Ty, Src2Ty,
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TargetOpcode::G_SELECT>
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m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
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return TernaryOp_match<Src0Ty, Src1Ty, Src2Ty,
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TargetOpcode::G_SELECT>(Src0, Src1, Src2);
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}
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/// Matches a register negated by a G_SUB.
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/// G_SUB 0, %negated_reg
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template <typename SrcTy>
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@ -484,6 +492,50 @@ m_Not(const SrcTy &&Src) {
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return m_GXor(Src, m_AllOnesInt());
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}
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// class that allows to match one of the following patterns:
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// select (pred, x, value1) -> cmp slt -> select (pred, origin, value2) ->
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// cmp sgt OR select (pred, x, value1) -> cmp sgt -> select (pred, origin,
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// value2) -> cmp slt
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// also binds the boundary values and the origin.
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template <typename Boundary1,
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typename Boundary2, typename Origin>
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struct MaxMin_match_helper {
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Boundary1 B1;
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Boundary2 B2;
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Origin O;
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MaxMin_match_helper(const Boundary1 &FirstBoundary,
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const Boundary2 &SecondBoundary, const Origin &Or)
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: B1(FirstBoundary), B2(SecondBoundary), O(Or) {}
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template <typename OpTy>
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bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
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CmpInst::Predicate Predicate1;
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Register Base;
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if (mi_match(Op, MRI,
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m_GISelect(m_GICmp(m_Pred(Predicate1), m_Reg(), m_Reg()),
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m_Reg(Base), B1))) {
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CmpInst::Predicate Predicate2;
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if (mi_match(Base, MRI, m_GISelect(m_GICmp(m_Pred(Predicate2), m_Reg(), m_Reg()), O, B2))) {
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if ((Predicate1 == CmpInst::ICMP_SLT && Predicate2 == CmpInst::ICMP_SGT) ||
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(Predicate1 == CmpInst::ICMP_SGT && Predicate2 == CmpInst::ICMP_SLT)) {
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return true;
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}
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}
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}
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return false;
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}
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};
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template <typename Boundary1, typename Boundary2, typename Origin>
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inline MaxMin_match_helper<Boundary1, Boundary2, Origin>
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m_MaxMin(const Boundary1 &B1, const Boundary2 &B2, const Origin &O) {
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return MaxMin_match_helper<Boundary1, Boundary2, Origin>(B1, B2, O);
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}
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} // namespace GMIPatternMatch
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} // namespace llvm
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@ -37,6 +37,14 @@ def cvt_f32_ubyteN : GICombineRule<
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[{ return PostLegalizerHelper.matchCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }]),
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(apply [{ PostLegalizerHelper.applyCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }])>;
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def clamp_i64_to_i16_matchdata : GIDefMatchData<"AMDGPUPostLegalizerCombinerHelper::ClampI64ToI16MatchInfo">;
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def clamp_i64_to_i16 : GICombineRule<
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(defs root:$clamp_i64_to_i16, clamp_i64_to_i16_matchdata:$matchinfo),
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(match (wip_match_opcode G_TRUNC):$clamp_i64_to_i16,
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[{ return PostLegalizerHelper.matchClampI64ToI16(*${clamp_i64_to_i16}, MRI, *MF, ${matchinfo}); }]),
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(apply [{ PostLegalizerHelper.applyClampI64ToI16(*${clamp_i64_to_i16}, ${matchinfo}); }])>;
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// Combines which should only apply on SI/VI
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def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>;
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@ -49,7 +57,7 @@ def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper<
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def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper<
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"AMDGPUGenPostLegalizerCombinerHelper",
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[all_combines, gfx6gfx7_combines,
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uchar_to_float, cvt_f32_ubyteN]> {
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uchar_to_float, cvt_f32_ubyteN, clamp_i64_to_i16]> {
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let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule";
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let StateClass = "AMDGPUPostLegalizerCombinerHelperState";
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let AdditionalArguments = [];
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@ -66,6 +66,19 @@ public:
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bool matchCvtF32UByteN(MachineInstr &MI, CvtF32UByteMatchInfo &MatchInfo);
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void applyCvtF32UByteN(MachineInstr &MI,
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const CvtF32UByteMatchInfo &MatchInfo);
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struct ClampI64ToI16MatchInfo {
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int64_t Cmp1;
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int64_t Cmp2;
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Register Origin;
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};
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bool matchClampI64ToI16(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineFunction &MF,
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ClampI64ToI16MatchInfo &MatchInfo);
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void applyClampI64ToI16(MachineInstr &MI,
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const ClampI64ToI16MatchInfo &MatchInfo);
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};
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bool AMDGPUPostLegalizerCombinerHelper::matchFMinFMaxLegacy(
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@ -245,6 +258,91 @@ void AMDGPUPostLegalizerCombinerHelper::applyCvtF32UByteN(
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MI.eraseFromParent();
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}
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bool AMDGPUPostLegalizerCombinerHelper::matchClampI64ToI16(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineFunction &MF,
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ClampI64ToI16MatchInfo &MatchInfo) {
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assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Invalid instruction!");
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const LLT SrcType = MRI.getType(MI.getOperand(1).getReg());
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if (SrcType != LLT::scalar(64))
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return false;
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MachineIRBuilder B(MI);
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LLVM_DEBUG(dbgs() << "Matching Clamp i64 to i16");
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if (mi_match(MI.getOperand(1).getReg(), MRI,
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m_MaxMin(m_ICst(MatchInfo.Cmp1),
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m_ICst(MatchInfo.Cmp2),
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m_Reg(MatchInfo.Origin)))) {
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const auto Cmp1 = static_cast<int64_t>(MatchInfo.Cmp1);
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const auto Cmp2 = static_cast<int64_t>(MatchInfo.Cmp2);
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const int64_t Min = static_cast<int64_t>(std::numeric_limits<int16_t>::min());
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const int64_t Max = static_cast<int64_t>(std::numeric_limits<int16_t>::max());
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// are we really trying to clamp against short boundaries?
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return ((Cmp2 >= Cmp1 && Cmp1 >= Min && Cmp2 <= Max) ||
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(Cmp1 >= Cmp2 && Cmp1 <= Max && Cmp2 >= Min));
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}
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return false;
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}
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void AMDGPUPostLegalizerCombinerHelper::applyClampI64ToI16(MachineInstr &MI,
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const ClampI64ToI16MatchInfo &MatchInfo) {
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LLVM_DEBUG(dbgs() << "Combining MI");
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MachineIRBuilder B(MI);
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MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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Register Src = MatchInfo.Origin;
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assert(MRI.getType(Src) == LLT::scalar(64));
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const LLT S32 = LLT::scalar(32);
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auto Unmerge = B.buildUnmerge(S32, Src);
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Register Hi32 = Unmerge->getOperand(0).getReg();
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Register Lo32 = Unmerge->getOperand(1).getReg();
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MRI.setRegClass(Hi32, &AMDGPU::VGPR_32RegClass);
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MRI.setRegClass(Lo32, &AMDGPU::VGPR_32RegClass);
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constexpr unsigned int CvtOpcode = AMDGPU::V_CVT_PK_I16_I32_e64;
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assert(MI.getOpcode() != CvtOpcode);
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Register CvtDst = MRI.createGenericVirtualRegister(S32);
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MRI.setRegClass(CvtDst, &AMDGPU::VGPR_32RegClass);
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auto CvtPk = B.buildInstr(CvtOpcode);
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CvtPk.addDef(CvtDst);
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CvtPk.addReg(Hi32);
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CvtPk.addReg(Lo32);
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CvtPk.setMIFlags(MI.getFlags());
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auto min = std::min(MatchInfo.Cmp1, MatchInfo.Cmp2);
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auto max = std::max(MatchInfo.Cmp1, MatchInfo.Cmp2);
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Register MinBoundaryDst = MRI.createGenericVirtualRegister(S32);
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MRI.setRegClass(MinBoundaryDst, &AMDGPU::VGPR_32RegClass);
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B.buildConstant(MinBoundaryDst, min);
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Register MaxBoundaryDst = MRI.createGenericVirtualRegister(S32);
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MRI.setRegClass(MaxBoundaryDst, &AMDGPU::VGPR_32RegClass);
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B.buildConstant(MaxBoundaryDst, max);
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Register MedDst = MRI.createGenericVirtualRegister(S32);
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MRI.setRegClass(MedDst, &AMDGPU::VGPR_32RegClass);
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auto Med = B.buildInstr(AMDGPU::V_MED3_I32);
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Med.addDef(MedDst);
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Med.addReg(MinBoundaryDst);
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Med.addReg(CvtDst);
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Med.addReg(MaxBoundaryDst);
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Med.setMIFlags(MI.getFlags());
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B.buildCopy(MI.getOperand(0).getReg(), MedDst);
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MI.eraseFromParent();
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}
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class AMDGPUPostLegalizerCombinerHelperState {
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protected:
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CombinerHelper &Helper;
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@ -0,0 +1,131 @@
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; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX678,GFX6789 %s
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; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9,GFX6789 %s
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; RUN: llc -global-isel -mcpu=gfx1010 -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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; GCN-LABEL: {{^}}v_clamp_i64_i16
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; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GFX6789: v_mov_b32_e32 [[B]], 0xffff8000
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; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
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; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
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; GCN: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GCN: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
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; GCN: v_med3_i32 [[A]], 0xffff8000, [[A]], [[C]]
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define i16 @v_clamp_i64_i16(i64 %in) nounwind {
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entry:
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%0 = icmp sgt i64 %in, -32768
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%1 = select i1 %0, i64 %in, i64 -32768
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%2 = icmp slt i64 %1, 32767
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%3 = select i1 %2, i64 %1, i64 32767
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%4 = trunc i64 %3 to i16
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ret i16 %4
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}
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; GCN-LABEL: {{^}}v_clamp_i64_i16_reverse
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; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GFX6789: v_mov_b32_e32 [[B]], 0xffff8000
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; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
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; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
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; GCN: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GCN: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
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; GCN: v_med3_i32 [[A]], 0xffff8000, [[A]], [[C]]
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define i16 @v_clamp_i64_i16_reverse(i64 %in) nounwind {
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entry:
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%0 = icmp slt i64 %in, 32767
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%1 = select i1 %0, i64 %in, i64 32767
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%2 = icmp sgt i64 %1, -32768
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%3 = select i1 %2, i64 %1, i64 -32768
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%4 = trunc i64 %3 to i16
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ret i16 %4
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}
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; GCN-LABEL: {{^}}v_clamp_i64_i16_wrong_lower
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; GFX6789: v_mov_b32_e32 [[B:v[0-9]+]], 0x8001
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; GFX6789: v_cndmask_b32_e32 [[A:v[0-9]+]], [[B]], [[A]], vcc
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; GFX6789: v_cndmask_b32_e32 [[C:v[0-9]+]], 0, [[C]], vcc
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; GCN: v_cndmask_b32_e32 [[A:v[0-9]+]], 0x8001, [[A]], vcc_lo
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; GCN: v_cndmask_b32_e32 [[B:v[0-9]+]], 0, [[B]], vcc_lo
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define i16 @v_clamp_i64_i16_wrong_lower(i64 %in) nounwind {
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entry:
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%0 = icmp slt i64 %in, 32769
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%1 = select i1 %0, i64 %in, i64 32769
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%2 = icmp sgt i64 %1, -32768
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%3 = select i1 %2, i64 %1, i64 -32768
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%4 = trunc i64 %3 to i16
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ret i16 %4
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}
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; GCN-LABEL: {{^}}v_clamp_i64_i16_wrong_lower_and_higher
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; GFX6789: v_mov_b32_e32 [[B:v[0-9]+]], 0x8000
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; GFX6789: v_cndmask_b32_e32 [[A:v[0-9]+]], [[B]], [[A]], vcc
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; GCN: v_cndmask_b32_e32 [[A:v[0-9]+]], 0x8000, [[A]], vcc_lo
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define i16 @v_clamp_i64_i16_wrong_lower_and_higher(i64 %in) nounwind {
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entry:
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%0 = icmp sgt i64 %in, -32769
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%1 = select i1 %0, i64 %in, i64 -32769
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%2 = icmp slt i64 %1, 32768
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%3 = select i1 %2, i64 %1, i64 32768
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%4 = trunc i64 %3 to i16
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ret i16 %4
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}
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; GCN-LABEL: {{^}}v_clamp_i64_i16_lower_than_short
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; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GFX6789: v_mov_b32_e32 [[B]], 0xffffff01
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; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
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; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
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; GCN: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GCN: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
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; GCN: v_med3_i32 [[A]], 0xffffff01, [[A]], [[C]]
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define i16 @v_clamp_i64_i16_lower_than_short(i64 %in) nounwind {
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entry:
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%0 = icmp slt i64 %in, 256
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%1 = select i1 %0, i64 %in, i64 256
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%2 = icmp sgt i64 %1, -255
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%3 = select i1 %2, i64 %1, i64 -255
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%4 = trunc i64 %3 to i16
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ret i16 %4
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}
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; GCN-LABEL: {{^}}v_clamp_i64_i16_lower_than_short_reverse
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; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GFX6789: v_mov_b32_e32 [[B]], 0xffffff01
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; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
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; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
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; GCN: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
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; GCN: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
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; GCN: v_med3_i32 [[A]], 0xffffff01, [[A]], [[C]]
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define i16 @v_clamp_i64_i16_lower_than_short_reverse(i64 %in) nounwind {
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entry:
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%0 = icmp sgt i64 %in, -255
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%1 = select i1 %0, i64 %in, i64 -255
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%2 = icmp slt i64 %1, 256
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%3 = select i1 %2, i64 %1, i64 256
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%4 = trunc i64 %3 to i16
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ret i16 %4
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}
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; GCN-LABEL: {{^}}v_clamp_i64_i16_zero
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; GFX678: v_mov_b32_e32 [[A:v[0-9]+]], 0
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; GCN: v_mov_b32_e32 [[A:v[0-9]+]], 0
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define i16 @v_clamp_i64_i16_zero(i64 %in) nounwind {
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entry:
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%0 = icmp sgt i64 %in, 0
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%1 = select i1 %0, i64 %in, i64 0
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%2 = icmp slt i64 %1, 0
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%3 = select i1 %2, i64 %1, i64 0
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%4 = trunc i64 %3 to i16
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ret i16 %4
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}
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