forked from OSchip/llvm-project
Added XOR instructions for rAX and immediates of
various widths. llvm-svn: 81458
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@ -1003,6 +1003,10 @@ def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
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"xor{q}\t{$src, $dst|$dst, $src}",
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[(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
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(implicit EFLAGS)]>;
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def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
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"xor{q}\t{$src, %rax|%rax, $src}", []>;
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} // Defs = [EFLAGS]
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//===----------------------------------------------------------------------===//
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@ -1895,6 +1895,13 @@ let isTwoAddress = 0 in {
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"xor{l}\t{$src, $dst|$dst, $src}",
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[(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
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(implicit EFLAGS)]>;
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def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
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"xor{b}\t{$src, %al|%al, $src}", []>;
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def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
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"xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
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def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
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"xor{l}\t{$src, %eax|%eax, $src}", []>;
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} // isTwoAddress = 0
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} // Defs = [EFLAGS]
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