forked from OSchip/llvm-project
[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling
This patch adds support for BigBitWidth -> SmallBitWidth bitcasts, splitting the DemandedBits/Elts accordingly. The AMDGPU backend needed an extra (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1) combine to encourage BFE creation, I investigated putting this in DAGCombine but it caused a lot of noise on other targets - some improvements, some regressions. The X86 changes are all definite wins. Differential Revision: https://reviews.llvm.org/D60462 llvm-svn: 358887
This commit is contained in:
Simon Pilgrim
parent
9bc6c77220
commit
6276ce0142
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@ -1467,6 +1467,30 @@ bool TargetLowering::SimplifyDemandedBits(
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KnownSrcZero, TLO, Depth + 1))
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return true;
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KnownBits KnownSrcBits;
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if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,
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KnownSrcBits, TLO, Depth + 1))
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return true;
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} else if ((NumSrcEltBits % BitWidth) == 0 &&
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TLO.DAG.getDataLayout().isLittleEndian()) {
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unsigned Scale = NumSrcEltBits / BitWidth;
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unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1;
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APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits);
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APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts);
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for (unsigned i = 0; i != NumElts; ++i)
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if (DemandedElts[i]) {
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unsigned Offset = (i % Scale) * BitWidth;
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DemandedSrcBits.insertBits(DemandedBits, Offset);
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DemandedSrcElts.setBit(i / Scale);
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}
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if (SrcVT.isVector()) {
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APInt KnownSrcUndef, KnownSrcZero;
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if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef,
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KnownSrcZero, TLO, Depth + 1))
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return true;
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}
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KnownBits KnownSrcBits;
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if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,
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KnownSrcBits, TLO, Depth + 1))
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@ -1476,7 +1500,7 @@ bool TargetLowering::SimplifyDemandedBits(
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// If this is a bitcast, let computeKnownBits handle it. Only do this on a
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// recursive call where Known may be useful to the caller.
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if (Depth > 0) {
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Known = TLO.DAG.computeKnownBits(Op, Depth);
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Known = TLO.DAG.computeKnownBits(Op, DemandedElts, Depth);
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return false;
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}
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break;
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@ -3147,30 +3147,44 @@ SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
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SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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if (N->getValueType(0) != MVT::i64)
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return SDValue();
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const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
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auto *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
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if (!RHS)
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return SDValue();
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EVT VT = N->getValueType(0);
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SDValue LHS = N->getOperand(0);
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unsigned ShiftAmt = RHS->getZExtValue();
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SelectionDAG &DAG = DCI.DAG;
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SDLoc SL(N);
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// fold (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1)
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// this improves the ability to match BFE patterns in isel.
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if (LHS.getOpcode() == ISD::AND) {
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if (auto *Mask = dyn_cast<ConstantSDNode>(LHS.getOperand(1))) {
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if (Mask->getAPIntValue().isShiftedMask() &&
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Mask->getAPIntValue().countTrailingZeros() == ShiftAmt) {
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return DAG.getNode(
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ISD::AND, SL, VT,
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DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(0), N->getOperand(1)),
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DAG.getNode(ISD::SRL, SL, VT, LHS.getOperand(1), N->getOperand(1)));
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}
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}
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}
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if (VT != MVT::i64)
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return SDValue();
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if (ShiftAmt < 32)
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return SDValue();
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// srl i64:x, C for C >= 32
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// =>
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// build_pair (srl hi_32(x), C - 32), 0
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SelectionDAG &DAG = DCI.DAG;
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SDLoc SL(N);
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SDValue One = DAG.getConstant(1, SL, MVT::i32);
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SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
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SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, N->getOperand(0));
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SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32,
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VecOp, One);
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SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, LHS);
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SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecOp, One);
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SDValue NewConst = DAG.getConstant(ShiftAmt - 32, SL, MVT::i32);
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SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);
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@ -86,8 +86,8 @@ define amdgpu_kernel void @local_store_i55(i55 addrspace(3)* %ptr, i55 %arg) #0
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; GFX9-NEXT: v_mov_b32_e32 v2, s2
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; GFX9-NEXT: ds_write_b16 v1, v2 offset:4
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v0, 0x7f0000, v0
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; GFX9-NEXT: ds_write_b8_d16_hi v1, v0 offset:6
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; GFX9-NEXT: v_bfe_u32 v0, v0, 16, 7
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; GFX9-NEXT: ds_write_b8 v1, v0 offset:6
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; GFX9-NEXT: ds_write_b32 v1, v3
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; GFX9-NEXT: s_endpgm
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store i55 %arg, i55 addrspace(3)* %ptr, align 8
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@ -448,22 +448,6 @@ define void @bitcast_8i32_store(i8* %p, <8 x i32> %a0) {
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define void @bitcast_4i64_store(i4* %p, <4 x i64> %a0) {
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; SSE2-SSSE3-LABEL: bitcast_4i64_store:
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; SSE2-SSSE3: # %bb.0:
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; SSE2-SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
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; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm1
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; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm3
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; SSE2-SSSE3-NEXT: pcmpeqd %xmm1, %xmm3
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; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm4
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; SSE2-SSSE3-NEXT: pcmpgtd %xmm1, %xmm4
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; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,0,2,2]
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; SSE2-SSSE3-NEXT: pand %xmm3, %xmm1
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; SSE2-SSSE3-NEXT: por %xmm4, %xmm1
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; SSE2-SSSE3-NEXT: pxor %xmm2, %xmm0
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; SSE2-SSSE3-NEXT: movdqa %xmm2, %xmm3
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; SSE2-SSSE3-NEXT: pcmpeqd %xmm0, %xmm3
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; SSE2-SSSE3-NEXT: pcmpgtd %xmm0, %xmm2
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; SSE2-SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]
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; SSE2-SSSE3-NEXT: pand %xmm3, %xmm0
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; SSE2-SSSE3-NEXT: por %xmm2, %xmm0
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; SSE2-SSSE3-NEXT: packssdw %xmm1, %xmm0
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; SSE2-SSSE3-NEXT: movmskps %xmm0, %eax
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; SSE2-SSSE3-NEXT: movb %al, (%rdi)
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@ -609,15 +609,13 @@ define void @bitcast_8i64_store(i8* %p, <8 x i64> %a0) {
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;
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; AVX1-LABEL: bitcast_8i64_store:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1
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; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0
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; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vmovmskps %ymm0, %eax
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; AVX1-NEXT: movb %al, (%rdi)
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@ -14,18 +14,11 @@ define i32 @t(i8* %ref_frame_ptr, i32 %ref_frame_stride, i32 %idxX, i32 %idxY) n
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;
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; X64-LABEL: t:
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; X64: ## %bb.0: ## %entry
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; X64-NEXT: ## kill: def $edx killed $edx def $rdx
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; X64-NEXT: ## kill: def $esi killed $esi def $rsi
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; X64-NEXT: imull %ecx, %esi
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; X64-NEXT: leal (%rsi,%rdx), %eax
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; X64-NEXT: cltq
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; X64-NEXT: addl %edx, %esi
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; X64-NEXT: movslq %esi, %rax
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; X64-NEXT: movl (%rdi,%rax), %eax
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; X64-NEXT: leal 4(%rsi,%rdx), %ecx
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; X64-NEXT: movslq %ecx, %rcx
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; X64-NEXT: movzwl (%rdi,%rcx), %ecx
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; X64-NEXT: shlq $32, %rcx
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; X64-NEXT: orq %rax, %rcx
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; X64-NEXT: movq %rcx, %xmm0
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; X64-NEXT: movq %rax, %xmm0
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; X64-NEXT: movd %xmm0, %eax
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; X64-NEXT: retq
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entry:
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@ -36,25 +36,21 @@ define void @store_v1f64_v1i64(<1 x i64> %trigger, <1 x double>* %addr, <1 x dou
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define void @store_v2f64_v2i64(<2 x i64> %trigger, <2 x double>* %addr, <2 x double> %val) {
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; SSE2-LABEL: store_v2f64_v2i64:
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; SSE2: ## %bb.0:
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; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
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; SSE2-NEXT: pxor %xmm3, %xmm0
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; SSE2-NEXT: movdqa %xmm3, %xmm2
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
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; SSE2-NEXT: pcmpeqd %xmm3, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; SSE2-NEXT: movdqa %xmm0, %xmm4
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; SSE2-NEXT: pand %xmm2, %xmm4
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
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; SSE2-NEXT: por %xmm3, %xmm4
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; SSE2-NEXT: movd %xmm4, %eax
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
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; SSE2-NEXT: pxor %xmm2, %xmm0
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; SSE2-NEXT: movdqa %xmm2, %xmm3
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm3
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; SSE2-NEXT: pcmpeqd %xmm2, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; SSE2-NEXT: pand %xmm3, %xmm2
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]
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; SSE2-NEXT: por %xmm2, %xmm0
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: testb $1, %al
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; SSE2-NEXT: je LBB1_2
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; SSE2-NEXT: ## %bb.1: ## %cond.store
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; SSE2-NEXT: movlpd %xmm1, (%rdi)
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; SSE2-NEXT: LBB1_2: ## %else
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
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; SSE2-NEXT: pand %xmm2, %xmm0
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; SSE2-NEXT: por %xmm3, %xmm0
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; SSE2-NEXT: pextrw $4, %xmm0, %eax
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; SSE2-NEXT: testb $1, %al
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; SSE2-NEXT: je LBB1_4
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@ -117,20 +113,16 @@ define void @store_v4f64_v4i64(<4 x i64> %trigger, <4 x double>* %addr, <4 x dou
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; SSE2-NEXT: movdqa %xmm4, %xmm5
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm5
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; SSE2-NEXT: pcmpeqd %xmm4, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; SSE2-NEXT: movdqa %xmm0, %xmm7
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; SSE2-NEXT: pand %xmm5, %xmm7
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; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[1,1,3,3]
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; SSE2-NEXT: por %xmm6, %xmm7
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; SSE2-NEXT: movd %xmm7, %eax
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; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3]
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; SSE2-NEXT: pand %xmm5, %xmm6
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3]
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; SSE2-NEXT: por %xmm6, %xmm0
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: testb $1, %al
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; SSE2-NEXT: je LBB2_2
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; SSE2-NEXT: ## %bb.1: ## %cond.store
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; SSE2-NEXT: movlpd %xmm2, (%rdi)
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; SSE2-NEXT: LBB2_2: ## %else
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; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,0,2,2]
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; SSE2-NEXT: pand %xmm5, %xmm0
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; SSE2-NEXT: por %xmm6, %xmm0
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; SSE2-NEXT: pextrw $4, %xmm0, %eax
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; SSE2-NEXT: testb $1, %al
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; SSE2-NEXT: je LBB2_4
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@ -140,10 +132,9 @@ define void @store_v4f64_v4i64(<4 x i64> %trigger, <4 x double>* %addr, <4 x dou
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; SSE2-NEXT: pxor %xmm4, %xmm1
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; SSE2-NEXT: movdqa %xmm4, %xmm0
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; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,2]
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; SSE2-NEXT: pcmpeqd %xmm4, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; SSE2-NEXT: pand %xmm2, %xmm1
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; SSE2-NEXT: pand %xmm0, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; SSE2-NEXT: por %xmm1, %xmm0
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; SSE2-NEXT: pextrw $0, %xmm0, %eax
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@ -863,25 +854,21 @@ define void @store_v16f32_v16i32(<16 x float> %x, <16 x float>* %ptr, <16 x floa
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define void @store_v2i64_v2i64(<2 x i64> %trigger, <2 x i64>* %addr, <2 x i64> %val) {
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; SSE2-LABEL: store_v2i64_v2i64:
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; SSE2: ## %bb.0:
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; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [2147483648,2147483648]
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; SSE2-NEXT: pxor %xmm3, %xmm0
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; SSE2-NEXT: movdqa %xmm3, %xmm2
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
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; SSE2-NEXT: pcmpeqd %xmm3, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; SSE2-NEXT: movdqa %xmm0, %xmm4
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; SSE2-NEXT: pand %xmm2, %xmm4
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
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; SSE2-NEXT: por %xmm3, %xmm4
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; SSE2-NEXT: movd %xmm4, %eax
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
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; SSE2-NEXT: pxor %xmm2, %xmm0
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; SSE2-NEXT: movdqa %xmm2, %xmm3
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm3
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; SSE2-NEXT: pcmpeqd %xmm2, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; SSE2-NEXT: pand %xmm3, %xmm2
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]
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; SSE2-NEXT: por %xmm2, %xmm0
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; SSE2-NEXT: movd %xmm0, %eax
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; SSE2-NEXT: testb $1, %al
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; SSE2-NEXT: je LBB7_2
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; SSE2-NEXT: ## %bb.1: ## %cond.store
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; SSE2-NEXT: movq %xmm1, (%rdi)
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; SSE2-NEXT: LBB7_2: ## %else
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,2,2]
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; SSE2-NEXT: pand %xmm2, %xmm0
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; SSE2-NEXT: por %xmm3, %xmm0
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; SSE2-NEXT: pextrw $4, %xmm0, %eax
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; SSE2-NEXT: testb $1, %al
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; SSE2-NEXT: je LBB7_4
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@ -950,20 +937,16 @@ define void @store_v4i64_v4i64(<4 x i64> %trigger, <4 x i64>* %addr, <4 x i64> %
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; SSE2-NEXT: movdqa %xmm4, %xmm5
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm5
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; SSE2-NEXT: pcmpeqd %xmm4, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; SSE2-NEXT: movdqa %xmm0, %xmm7
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; SSE2-NEXT: pand %xmm5, %xmm7
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; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm5[1,1,3,3]
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; SSE2-NEXT: por %xmm6, %xmm7
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; SSE2-NEXT: movd %xmm7, %eax
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; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3]
|
||||
; SSE2-NEXT: pand %xmm5, %xmm6
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3]
|
||||
; SSE2-NEXT: por %xmm6, %xmm0
|
||||
; SSE2-NEXT: movd %xmm0, %eax
|
||||
; SSE2-NEXT: testb $1, %al
|
||||
; SSE2-NEXT: je LBB8_2
|
||||
; SSE2-NEXT: ## %bb.1: ## %cond.store
|
||||
; SSE2-NEXT: movq %xmm2, (%rdi)
|
||||
; SSE2-NEXT: LBB8_2: ## %else
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,0,2,2]
|
||||
; SSE2-NEXT: pand %xmm5, %xmm0
|
||||
; SSE2-NEXT: por %xmm6, %xmm0
|
||||
; SSE2-NEXT: pextrw $4, %xmm0, %eax
|
||||
; SSE2-NEXT: testb $1, %al
|
||||
; SSE2-NEXT: je LBB8_4
|
||||
|
|
@ -974,10 +957,9 @@ define void @store_v4i64_v4i64(<4 x i64> %trigger, <4 x i64>* %addr, <4 x i64> %
|
|||
; SSE2-NEXT: pxor %xmm4, %xmm1
|
||||
; SSE2-NEXT: movdqa %xmm4, %xmm0
|
||||
; SSE2-NEXT: pcmpgtd %xmm1, %xmm0
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,2]
|
||||
; SSE2-NEXT: pcmpeqd %xmm4, %xmm1
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; SSE2-NEXT: pand %xmm2, %xmm1
|
||||
; SSE2-NEXT: pand %xmm0, %xmm1
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
|
||||
; SSE2-NEXT: por %xmm1, %xmm0
|
||||
; SSE2-NEXT: pextrw $0, %xmm0, %eax
|
||||
|
|
|
|||
|
|
@ -929,22 +929,6 @@ define i1 @allzeros_v16i32_sign(<16 x i32> %arg) {
|
|||
define i1 @allones_v4i64_sign(<4 x i64> %arg) {
|
||||
; SSE2-LABEL: allones_v4i64_sign:
|
||||
; SSE2: # %bb.0:
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
|
||||
; SSE2-NEXT: pxor %xmm2, %xmm1
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm3
|
||||
; SSE2-NEXT: pcmpeqd %xmm1, %xmm3
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm4
|
||||
; SSE2-NEXT: pcmpgtd %xmm1, %xmm4
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,0,2,2]
|
||||
; SSE2-NEXT: pand %xmm3, %xmm1
|
||||
; SSE2-NEXT: por %xmm4, %xmm1
|
||||
; SSE2-NEXT: pxor %xmm2, %xmm0
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm3
|
||||
; SSE2-NEXT: pcmpeqd %xmm0, %xmm3
|
||||
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]
|
||||
; SSE2-NEXT: pand %xmm3, %xmm0
|
||||
; SSE2-NEXT: por %xmm2, %xmm0
|
||||
; SSE2-NEXT: packssdw %xmm1, %xmm0
|
||||
; SSE2-NEXT: movmskps %xmm0, %eax
|
||||
; SSE2-NEXT: cmpb $15, %al
|
||||
|
|
@ -989,22 +973,6 @@ define i1 @allones_v4i64_sign(<4 x i64> %arg) {
|
|||
define i1 @allzeros_v4i64_sign(<4 x i64> %arg) {
|
||||
; SSE2-LABEL: allzeros_v4i64_sign:
|
||||
; SSE2: # %bb.0:
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
|
||||
; SSE2-NEXT: pxor %xmm2, %xmm1
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm3
|
||||
; SSE2-NEXT: pcmpeqd %xmm1, %xmm3
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm4
|
||||
; SSE2-NEXT: pcmpgtd %xmm1, %xmm4
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,0,2,2]
|
||||
; SSE2-NEXT: pand %xmm3, %xmm1
|
||||
; SSE2-NEXT: por %xmm4, %xmm1
|
||||
; SSE2-NEXT: pxor %xmm2, %xmm0
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm3
|
||||
; SSE2-NEXT: pcmpeqd %xmm0, %xmm3
|
||||
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]
|
||||
; SSE2-NEXT: pand %xmm3, %xmm0
|
||||
; SSE2-NEXT: por %xmm2, %xmm0
|
||||
; SSE2-NEXT: packssdw %xmm1, %xmm0
|
||||
; SSE2-NEXT: movmskps %xmm0, %eax
|
||||
; SSE2-NEXT: testb %al, %al
|
||||
|
|
@ -1095,15 +1063,13 @@ define i1 @allones_v8i64_sign(<8 x i64> %arg) {
|
|||
;
|
||||
; AVX1-LABEL: allones_v8i64_sign:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vmovmskps %ymm0, %eax
|
||||
; AVX1-NEXT: cmpb $-1, %al
|
||||
|
|
@ -1198,15 +1164,13 @@ define i1 @allzeros_v8i64_sign(<8 x i64> %arg) {
|
|||
;
|
||||
; AVX1-LABEL: allzeros_v8i64_sign:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vmovmskps %ymm0, %eax
|
||||
; AVX1-NEXT: testb %al, %al
|
||||
|
|
@ -2539,19 +2503,17 @@ define i1 @allones_v8i64_and1(<8 x i64> %arg) {
|
|||
;
|
||||
; AVX1-LABEL: allones_v8i64_and1:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vmovmskps %ymm0, %eax
|
||||
; AVX1-NEXT: cmpb $-1, %al
|
||||
|
|
@ -2615,19 +2577,17 @@ define i1 @allzeros_v8i64_and1(<8 x i64> %arg) {
|
|||
;
|
||||
; AVX1-LABEL: allzeros_v8i64_and1:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsllq $63, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vmovmskps %ymm0, %eax
|
||||
; AVX1-NEXT: testb %al, %al
|
||||
|
|
@ -3962,19 +3922,17 @@ define i1 @allones_v8i64_and4(<8 x i64> %arg) {
|
|||
;
|
||||
; AVX1-LABEL: allones_v8i64_and4:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vmovmskps %ymm0, %eax
|
||||
; AVX1-NEXT: cmpb $-1, %al
|
||||
|
|
@ -4038,19 +3996,17 @@ define i1 @allzeros_v8i64_and4(<8 x i64> %arg) {
|
|||
;
|
||||
; AVX1-LABEL: allzeros_v8i64_and4:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsllq $61, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vmovmskps %ymm0, %eax
|
||||
; AVX1-NEXT: testb %al, %al
|
||||
|
|
@ -4170,22 +4126,6 @@ define i32 @movmskps(<4 x float> %x) {
|
|||
define i32 @movmskpd256(<4 x double> %x) {
|
||||
; SSE2-LABEL: movmskpd256:
|
||||
; SSE2: # %bb.0:
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648]
|
||||
; SSE2-NEXT: pxor %xmm2, %xmm1
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm3
|
||||
; SSE2-NEXT: pcmpeqd %xmm1, %xmm3
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm4
|
||||
; SSE2-NEXT: pcmpgtd %xmm1, %xmm4
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,0,2,2]
|
||||
; SSE2-NEXT: pand %xmm3, %xmm1
|
||||
; SSE2-NEXT: por %xmm4, %xmm1
|
||||
; SSE2-NEXT: pxor %xmm2, %xmm0
|
||||
; SSE2-NEXT: movdqa %xmm2, %xmm3
|
||||
; SSE2-NEXT: pcmpeqd %xmm0, %xmm3
|
||||
; SSE2-NEXT: pcmpgtd %xmm0, %xmm2
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,0,2,2]
|
||||
; SSE2-NEXT: pand %xmm3, %xmm0
|
||||
; SSE2-NEXT: por %xmm2, %xmm0
|
||||
; SSE2-NEXT: packssdw %xmm1, %xmm0
|
||||
; SSE2-NEXT: movmskps %xmm0, %eax
|
||||
; SSE2-NEXT: retq
|
||||
|
|
|
|||
Loading…
Reference in New Issue