forked from OSchip/llvm-project
Directly access objects which may change during compilation.
llvm-svn: 184121
This commit is contained in:
parent
702a80c72f
commit
626c991ce9
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@ -132,15 +132,17 @@ public:
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/// address of the function constant pool values.
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/// address of the function constant pool values.
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/// @brief The machine constant pool.
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/// @brief The machine constant pool.
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class MachineConstantPool {
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class MachineConstantPool {
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const DataLayout *TD; ///< The machine's DataLayout.
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const TargetMachine &TM; ///< The target machine.
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unsigned PoolAlignment; ///< The alignment for the pool.
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unsigned PoolAlignment; ///< The alignment for the pool.
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std::vector<MachineConstantPoolEntry> Constants; ///< The pool of constants.
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std::vector<MachineConstantPoolEntry> Constants; ///< The pool of constants.
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/// MachineConstantPoolValues that use an existing MachineConstantPoolEntry.
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/// MachineConstantPoolValues that use an existing MachineConstantPoolEntry.
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DenseSet<MachineConstantPoolValue*> MachineCPVsSharingEntries;
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DenseSet<MachineConstantPoolValue*> MachineCPVsSharingEntries;
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const DataLayout *getDataLayout() const;
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public:
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public:
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/// @brief The only constructor.
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/// @brief The only constructor.
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explicit MachineConstantPool(const DataLayout *td)
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explicit MachineConstantPool(const TargetMachine &TM)
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: TD(td), PoolAlignment(1) {}
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: TM(TM), PoolAlignment(1) {}
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~MachineConstantPool();
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~MachineConstantPool();
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/// getConstantPoolAlignment - Return the alignment required by
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/// getConstantPoolAlignment - Return the alignment required by
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@ -27,6 +27,7 @@ class Type;
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class MachineFunction;
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class MachineFunction;
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class MachineBasicBlock;
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class MachineBasicBlock;
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class TargetFrameLowering;
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class TargetFrameLowering;
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class TargetMachine;
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class BitVector;
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class BitVector;
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class Value;
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class Value;
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class AllocaInst;
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class AllocaInst;
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@ -119,6 +120,8 @@ class MachineFrameInfo {
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isSpillSlot(isSS), MayNeedSP(NSP), Alloca(Val), PreAllocated(false) {}
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isSpillSlot(isSS), MayNeedSP(NSP), Alloca(Val), PreAllocated(false) {}
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};
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};
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const TargetMachine &TM;
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/// Objects - The list of stack objects allocated...
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/// Objects - The list of stack objects allocated...
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///
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///
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std::vector<StackObject> Objects;
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std::vector<StackObject> Objects;
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@ -201,10 +204,6 @@ class MachineFrameInfo {
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/// CSIValid - Has CSInfo been set yet?
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/// CSIValid - Has CSInfo been set yet?
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bool CSIValid;
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bool CSIValid;
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/// TargetFrameLowering - Target information about frame layout.
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///
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const TargetFrameLowering &TFI;
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/// LocalFrameObjects - References to frame indices which are mapped
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/// LocalFrameObjects - References to frame indices which are mapped
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/// into the local frame allocation block. <FrameIdx, LocalOffset>
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/// into the local frame allocation block. <FrameIdx, LocalOffset>
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SmallVector<std::pair<int, int64_t>, 32> LocalFrameObjects;
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SmallVector<std::pair<int, int64_t>, 32> LocalFrameObjects;
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@ -223,9 +222,11 @@ class MachineFrameInfo {
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/// Whether the "realign-stack" option is on.
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/// Whether the "realign-stack" option is on.
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bool RealignOption;
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bool RealignOption;
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const TargetFrameLowering *getFrameLowering() const;
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public:
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public:
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explicit MachineFrameInfo(const TargetFrameLowering &tfi, bool RealignOpt)
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explicit MachineFrameInfo(const TargetMachine &TM, bool RealignOpt)
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: TFI(tfi), RealignOption(RealignOpt) {
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: TM(TM), RealignOption(RealignOpt) {
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StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0;
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StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0;
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HasVarSizedObjects = false;
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HasVarSizedObjects = false;
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FrameAddressTaken = false;
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FrameAddressTaken = false;
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@ -17,6 +17,7 @@
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <vector>
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#include <vector>
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@ -26,7 +27,7 @@ namespace llvm {
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/// registers, including vreg register classes, use/def chains for registers,
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/// registers, including vreg register classes, use/def chains for registers,
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/// etc.
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/// etc.
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class MachineRegisterInfo {
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class MachineRegisterInfo {
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const TargetRegisterInfo *const TRI;
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const TargetMachine &TM;
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/// IsSSA - True when the machine function is in SSA form and virtual
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/// IsSSA - True when the machine function is in SSA form and virtual
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/// registers have a single def.
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/// registers have a single def.
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@ -57,6 +58,10 @@ class MachineRegisterInfo {
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/// physical registers.
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/// physical registers.
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MachineOperand **PhysRegUseDefLists;
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MachineOperand **PhysRegUseDefLists;
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const TargetRegisterInfo *getTargetRegisterInfo() const {
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return TM.getRegisterInfo();
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}
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/// getRegUseDefListHead - Return the head pointer for the register use/def
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/// getRegUseDefListHead - Return the head pointer for the register use/def
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/// list for the specified virtual or physical register.
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/// list for the specified virtual or physical register.
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MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
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MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
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@ -108,7 +113,7 @@ class MachineRegisterInfo {
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MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
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MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
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void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
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void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
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public:
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public:
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explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
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explicit MachineRegisterInfo(const TargetMachine &TM);
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~MachineRegisterInfo();
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~MachineRegisterInfo();
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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@ -377,7 +382,8 @@ public:
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bool isPhysRegUsed(unsigned Reg) const {
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bool isPhysRegUsed(unsigned Reg) const {
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if (UsedPhysRegMask.test(Reg))
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if (UsedPhysRegMask.test(Reg))
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return true;
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return true;
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for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
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for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
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Units.isValid(); ++Units)
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if (UsedRegUnits.test(*Units))
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if (UsedRegUnits.test(*Units))
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return true;
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return true;
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return false;
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return false;
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@ -392,7 +398,8 @@ public:
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/// setPhysRegUsed - Mark the specified register used in this function.
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/// setPhysRegUsed - Mark the specified register used in this function.
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/// This should only be called during and after register allocation.
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/// This should only be called during and after register allocation.
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void setPhysRegUsed(unsigned Reg) {
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void setPhysRegUsed(unsigned Reg) {
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for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
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for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
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Units.isValid(); ++Units)
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UsedRegUnits.set(*Units);
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UsedRegUnits.set(*Units);
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}
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}
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@ -406,7 +413,8 @@ public:
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/// This should only be called during and after register allocation.
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/// This should only be called during and after register allocation.
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void setPhysRegUnused(unsigned Reg) {
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void setPhysRegUnused(unsigned Reg) {
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UsedPhysRegMask.reset(Reg);
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UsedPhysRegMask.reset(Reg);
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for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
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for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
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Units.isValid(); ++Units)
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UsedRegUnits.reset(*Units);
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UsedRegUnits.reset(*Units);
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}
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}
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@ -466,7 +474,8 @@ public:
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/// register, so a register allocator needs to track its liveness and
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/// register, so a register allocator needs to track its liveness and
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/// availability.
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/// availability.
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bool isAllocatable(unsigned PhysReg) const {
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bool isAllocatable(unsigned PhysReg) const {
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return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
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return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
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!isReserved(PhysReg);
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}
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}
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//===--------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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void resetTargetOptions(const MachineFunction *MF) const;
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void resetTargetOptions(const MachineFunction *MF) const;
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// Interfaces to the major aspects of target machine information:
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// Interfaces to the major aspects of target machine information:
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//
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// -- Instruction opcode and operand information
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// -- Instruction opcode and operand information
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// -- Pipelines and scheduling information
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// -- Pipelines and scheduling information
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// -- Stack frame information
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// -- Stack frame information
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// -- Selection DAG lowering information
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// -- Selection DAG lowering information
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//
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//
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// N.B. These objects may change during compilation. It's not safe to cache
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// them between functions.
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virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
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virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
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virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
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virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
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virtual const TargetLowering *getTargetLowering() const { return 0; }
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virtual const TargetLowering *getTargetLowering() const { return 0; }
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@ -55,23 +55,27 @@ MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM,
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GCModuleInfo* gmi)
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GCModuleInfo* gmi)
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: Fn(F), Target(TM), Ctx(mmi.getContext()), MMI(mmi), GMI(gmi) {
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: Fn(F), Target(TM), Ctx(mmi.getContext()), MMI(mmi), GMI(gmi) {
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if (TM.getRegisterInfo())
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if (TM.getRegisterInfo())
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RegInfo = new (Allocator) MachineRegisterInfo(*TM.getRegisterInfo());
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RegInfo = new (Allocator) MachineRegisterInfo(TM);
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else
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else
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RegInfo = 0;
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RegInfo = 0;
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MFInfo = 0;
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MFInfo = 0;
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FrameInfo = new (Allocator) MachineFrameInfo(*TM.getFrameLowering(),
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FrameInfo = new (Allocator) MachineFrameInfo(TM, TM.Options.RealignStack);
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TM.Options.RealignStack);
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if (Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
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if (Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
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Attribute::StackAlignment))
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Attribute::StackAlignment))
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FrameInfo->ensureMaxAlignment(Fn->getAttributes().
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FrameInfo->ensureMaxAlignment(Fn->getAttributes().
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getStackAlignment(AttributeSet::FunctionIndex));
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getStackAlignment(AttributeSet::FunctionIndex));
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ConstantPool = new (Allocator) MachineConstantPool(TM.getDataLayout());
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ConstantPool = new (Allocator) MachineConstantPool(TM);
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Alignment = TM.getTargetLowering()->getMinFunctionAlignment();
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Alignment = TM.getTargetLowering()->getMinFunctionAlignment();
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// FIXME: Shouldn't use pref alignment if explicit alignment is set on Fn.
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// FIXME: Shouldn't use pref alignment if explicit alignment is set on Fn.
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if (!Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
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if (!Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
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Attribute::OptimizeForSize))
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Attribute::OptimizeForSize))
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Alignment = std::max(Alignment,
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Alignment = std::max(Alignment,
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TM.getTargetLowering()->getPrefFunctionAlignment());
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TM.getTargetLowering()->getPrefFunctionAlignment());
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FunctionNumber = FunctionNum;
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FunctionNumber = FunctionNum;
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JumpTableInfo = 0;
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JumpTableInfo = 0;
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}
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}
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@ -457,11 +461,15 @@ MCSymbol *MachineFunction::getPICBaseSymbol() const {
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// MachineFrameInfo implementation
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// MachineFrameInfo implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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const TargetFrameLowering *MachineFrameInfo::getFrameLowering() const {
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return TM.getFrameLowering();
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}
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/// ensureMaxAlignment - Make sure the function is at least Align bytes
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/// ensureMaxAlignment - Make sure the function is at least Align bytes
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/// aligned.
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/// aligned.
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void MachineFrameInfo::ensureMaxAlignment(unsigned Align) {
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void MachineFrameInfo::ensureMaxAlignment(unsigned Align) {
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if (!TFI.isStackRealignable() || !RealignOption)
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if (!getFrameLowering()->isStackRealignable() || !RealignOption)
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assert(Align <= TFI.getStackAlignment() &&
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assert(Align <= getFrameLowering()->getStackAlignment() &&
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"For targets without stack realignment, Align is out of limit!");
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"For targets without stack realignment, Align is out of limit!");
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if (MaxAlignment < Align) MaxAlignment = Align;
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if (MaxAlignment < Align) MaxAlignment = Align;
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}
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}
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@ -483,8 +491,10 @@ static inline unsigned clampStackAlignment(bool ShouldClamp, unsigned Align,
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int MachineFrameInfo::CreateStackObject(uint64_t Size, unsigned Alignment,
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int MachineFrameInfo::CreateStackObject(uint64_t Size, unsigned Alignment,
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bool isSS, bool MayNeedSP, const AllocaInst *Alloca) {
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bool isSS, bool MayNeedSP, const AllocaInst *Alloca) {
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assert(Size != 0 && "Cannot allocate zero size stack objects!");
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assert(Size != 0 && "Cannot allocate zero size stack objects!");
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Alignment = clampStackAlignment(!TFI.isStackRealignable() || !RealignOption,
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Alignment =
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Alignment, TFI.getStackAlignment());
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clampStackAlignment(!getFrameLowering()->isStackRealignable() ||
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!RealignOption,
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Alignment, getFrameLowering()->getStackAlignment());
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Objects.push_back(StackObject(Size, Alignment, 0, false, isSS, MayNeedSP,
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Objects.push_back(StackObject(Size, Alignment, 0, false, isSS, MayNeedSP,
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Alloca));
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Alloca));
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int Index = (int)Objects.size() - NumFixedObjects - 1;
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int Index = (int)Objects.size() - NumFixedObjects - 1;
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@ -499,8 +509,10 @@ int MachineFrameInfo::CreateStackObject(uint64_t Size, unsigned Alignment,
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///
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///
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int MachineFrameInfo::CreateSpillStackObject(uint64_t Size,
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int MachineFrameInfo::CreateSpillStackObject(uint64_t Size,
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unsigned Alignment) {
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unsigned Alignment) {
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Alignment = clampStackAlignment(!TFI.isStackRealignable() || !RealignOption,
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Alignment =
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Alignment, TFI.getStackAlignment());
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clampStackAlignment(!getFrameLowering()->isStackRealignable() ||
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!RealignOption,
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Alignment, getFrameLowering()->getStackAlignment());
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CreateStackObject(Size, Alignment, true, false);
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CreateStackObject(Size, Alignment, true, false);
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int Index = (int)Objects.size() - NumFixedObjects - 1;
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int Index = (int)Objects.size() - NumFixedObjects - 1;
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ensureMaxAlignment(Alignment);
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ensureMaxAlignment(Alignment);
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///
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///
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int MachineFrameInfo::CreateVariableSizedObject(unsigned Alignment) {
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int MachineFrameInfo::CreateVariableSizedObject(unsigned Alignment) {
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HasVarSizedObjects = true;
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HasVarSizedObjects = true;
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Alignment = clampStackAlignment(!TFI.isStackRealignable() || !RealignOption,
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Alignment =
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Alignment, TFI.getStackAlignment());
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clampStackAlignment(!getFrameLowering()->isStackRealignable() ||
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!RealignOption,
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Alignment, getFrameLowering()->getStackAlignment());
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Objects.push_back(StackObject(0, Alignment, 0, false, false, true, 0));
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Objects.push_back(StackObject(0, Alignment, 0, false, false, true, 0));
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ensureMaxAlignment(Alignment);
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ensureMaxAlignment(Alignment);
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return (int)Objects.size()-NumFixedObjects-1;
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return (int)Objects.size()-NumFixedObjects-1;
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@ -533,10 +547,12 @@ int MachineFrameInfo::CreateFixedObject(uint64_t Size, int64_t SPOffset,
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// the incoming frame position. If the frame object is at offset 32 and
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// the incoming frame position. If the frame object is at offset 32 and
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// the stack is guaranteed to be 16-byte aligned, then we know that the
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// the stack is guaranteed to be 16-byte aligned, then we know that the
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// object is 16-byte aligned.
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// object is 16-byte aligned.
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unsigned StackAlign = TFI.getStackAlignment();
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unsigned StackAlign = getFrameLowering()->getStackAlignment();
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unsigned Align = MinAlign(SPOffset, StackAlign);
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unsigned Align = MinAlign(SPOffset, StackAlign);
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Align = clampStackAlignment(!TFI.isStackRealignable() || !RealignOption,
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Align =
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Align, TFI.getStackAlignment());
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clampStackAlignment(!getFrameLowering()->isStackRealignable() ||
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!RealignOption,
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Align, getFrameLowering()->getStackAlignment());
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Objects.insert(Objects.begin(), StackObject(Size, Align, SPOffset, Immutable,
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Objects.insert(Objects.begin(), StackObject(Size, Align, SPOffset, Immutable,
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/*isSS*/ false,
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/*isSS*/ false,
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/*NeedSP*/ false,
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/*NeedSP*/ false,
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@ -770,6 +786,10 @@ void MachineJumpTableInfo::dump() const { print(dbgs()); }
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void MachineConstantPoolValue::anchor() { }
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void MachineConstantPoolValue::anchor() { }
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const DataLayout *MachineConstantPool::getDataLayout() const {
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return TM.getDataLayout();
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}
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Type *MachineConstantPoolEntry::getType() const {
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Type *MachineConstantPoolEntry::getType() const {
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if (isMachineConstantPoolEntry())
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if (isMachineConstantPoolEntry())
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return Val.MachineCPVal->getType();
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return Val.MachineCPVal->getType();
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@ -851,7 +871,8 @@ unsigned MachineConstantPool::getConstantPoolIndex(const Constant *C,
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// FIXME, this could be made much more efficient for large constant pools.
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// FIXME, this could be made much more efficient for large constant pools.
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for (unsigned i = 0, e = Constants.size(); i != e; ++i)
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for (unsigned i = 0, e = Constants.size(); i != e; ++i)
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if (!Constants[i].isMachineConstantPoolEntry() &&
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if (!Constants[i].isMachineConstantPoolEntry() &&
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CanShareConstantPoolEntry(Constants[i].Val.ConstVal, C, TD)) {
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CanShareConstantPoolEntry(Constants[i].Val.ConstVal, C,
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getDataLayout())) {
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if ((unsigned)Constants[i].getAlignment() < Alignment)
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if ((unsigned)Constants[i].getAlignment() < Alignment)
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Constants[i].Alignment = Alignment;
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Constants[i].Alignment = Alignment;
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return i;
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return i;
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@ -19,16 +19,18 @@
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using namespace llvm;
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using namespace llvm;
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MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI)
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MachineRegisterInfo::MachineRegisterInfo(const TargetMachine &TM)
|
||||||
: TRI(&TRI), IsSSA(true), TracksLiveness(true) {
|
: TM(TM), IsSSA(true), TracksLiveness(true) {
|
||||||
VRegInfo.reserve(256);
|
VRegInfo.reserve(256);
|
||||||
RegAllocHints.reserve(256);
|
RegAllocHints.reserve(256);
|
||||||
UsedRegUnits.resize(TRI.getNumRegUnits());
|
UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits());
|
||||||
UsedPhysRegMask.resize(TRI.getNumRegs());
|
UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
|
||||||
|
|
||||||
// Create the physreg use/def lists.
|
// Create the physreg use/def lists.
|
||||||
PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
|
PhysRegUseDefLists =
|
||||||
memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
|
new MachineOperand*[getTargetRegisterInfo()->getNumRegs()];
|
||||||
|
memset(PhysRegUseDefLists, 0,
|
||||||
|
sizeof(MachineOperand*)*getTargetRegisterInfo()->getNumRegs());
|
||||||
}
|
}
|
||||||
|
|
||||||
MachineRegisterInfo::~MachineRegisterInfo() {
|
MachineRegisterInfo::~MachineRegisterInfo() {
|
||||||
|
@ -50,7 +52,8 @@ MachineRegisterInfo::constrainRegClass(unsigned Reg,
|
||||||
const TargetRegisterClass *OldRC = getRegClass(Reg);
|
const TargetRegisterClass *OldRC = getRegClass(Reg);
|
||||||
if (OldRC == RC)
|
if (OldRC == RC)
|
||||||
return RC;
|
return RC;
|
||||||
const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
|
const TargetRegisterClass *NewRC =
|
||||||
|
getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
|
||||||
if (!NewRC || NewRC == OldRC)
|
if (!NewRC || NewRC == OldRC)
|
||||||
return NewRC;
|
return NewRC;
|
||||||
if (NewRC->getNumRegs() < MinNumRegs)
|
if (NewRC->getNumRegs() < MinNumRegs)
|
||||||
|
@ -63,7 +66,8 @@ bool
|
||||||
MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
|
MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
|
||||||
const TargetInstrInfo *TII = TM.getInstrInfo();
|
const TargetInstrInfo *TII = TM.getInstrInfo();
|
||||||
const TargetRegisterClass *OldRC = getRegClass(Reg);
|
const TargetRegisterClass *OldRC = getRegClass(Reg);
|
||||||
const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC);
|
const TargetRegisterClass *NewRC =
|
||||||
|
getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC);
|
||||||
|
|
||||||
// Stop early if there is no room to grow.
|
// Stop early if there is no room to grow.
|
||||||
if (NewRC == OldRC)
|
if (NewRC == OldRC)
|
||||||
|
@ -73,14 +77,16 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
|
||||||
for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
|
for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
|
||||||
++I) {
|
++I) {
|
||||||
const TargetRegisterClass *OpRC =
|
const TargetRegisterClass *OpRC =
|
||||||
I->getRegClassConstraint(I.getOperandNo(), TII, TRI);
|
I->getRegClassConstraint(I.getOperandNo(), TII,
|
||||||
|
getTargetRegisterInfo());
|
||||||
if (unsigned SubIdx = I.getOperand().getSubReg()) {
|
if (unsigned SubIdx = I.getOperand().getSubReg()) {
|
||||||
if (OpRC)
|
if (OpRC)
|
||||||
NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
|
NewRC = getTargetRegisterInfo()->getMatchingSuperRegClass(NewRC, OpRC,
|
||||||
|
SubIdx);
|
||||||
else
|
else
|
||||||
NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
|
NewRC = getTargetRegisterInfo()->getSubClassWithSubReg(NewRC, SubIdx);
|
||||||
} else if (OpRC)
|
} else if (OpRC)
|
||||||
NewRC = TRI->getCommonSubClass(NewRC, OpRC);
|
NewRC = getTargetRegisterInfo()->getCommonSubClass(NewRC, OpRC);
|
||||||
if (!NewRC || NewRC == OldRC)
|
if (!NewRC || NewRC == OldRC)
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
@ -126,24 +132,28 @@ void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
|
||||||
MachineOperand *MO = &I.getOperand();
|
MachineOperand *MO = &I.getOperand();
|
||||||
MachineInstr *MI = MO->getParent();
|
MachineInstr *MI = MO->getParent();
|
||||||
if (!MI) {
|
if (!MI) {
|
||||||
errs() << PrintReg(Reg, TRI) << " use list MachineOperand " << MO
|
errs() << PrintReg(Reg, getTargetRegisterInfo())
|
||||||
|
<< " use list MachineOperand " << MO
|
||||||
<< " has no parent instruction.\n";
|
<< " has no parent instruction.\n";
|
||||||
Valid = false;
|
Valid = false;
|
||||||
}
|
}
|
||||||
MachineOperand *MO0 = &MI->getOperand(0);
|
MachineOperand *MO0 = &MI->getOperand(0);
|
||||||
unsigned NumOps = MI->getNumOperands();
|
unsigned NumOps = MI->getNumOperands();
|
||||||
if (!(MO >= MO0 && MO < MO0+NumOps)) {
|
if (!(MO >= MO0 && MO < MO0+NumOps)) {
|
||||||
errs() << PrintReg(Reg, TRI) << " use list MachineOperand " << MO
|
errs() << PrintReg(Reg, getTargetRegisterInfo())
|
||||||
|
<< " use list MachineOperand " << MO
|
||||||
<< " doesn't belong to parent MI: " << *MI;
|
<< " doesn't belong to parent MI: " << *MI;
|
||||||
Valid = false;
|
Valid = false;
|
||||||
}
|
}
|
||||||
if (!MO->isReg()) {
|
if (!MO->isReg()) {
|
||||||
errs() << PrintReg(Reg, TRI) << " MachineOperand " << MO << ": " << *MO
|
errs() << PrintReg(Reg, getTargetRegisterInfo())
|
||||||
|
<< " MachineOperand " << MO << ": " << *MO
|
||||||
<< " is not a register\n";
|
<< " is not a register\n";
|
||||||
Valid = false;
|
Valid = false;
|
||||||
}
|
}
|
||||||
if (MO->getReg() != Reg) {
|
if (MO->getReg() != Reg) {
|
||||||
errs() << PrintReg(Reg, TRI) << " use-list MachineOperand " << MO << ": "
|
errs() << PrintReg(Reg, getTargetRegisterInfo())
|
||||||
|
<< " use-list MachineOperand " << MO << ": "
|
||||||
<< *MO << " is the wrong register\n";
|
<< *MO << " is the wrong register\n";
|
||||||
Valid = false;
|
Valid = false;
|
||||||
}
|
}
|
||||||
|
@ -156,7 +166,7 @@ void MachineRegisterInfo::verifyUseLists() const {
|
||||||
#ifndef NDEBUG
|
#ifndef NDEBUG
|
||||||
for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
|
for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
|
||||||
verifyUseList(TargetRegisterInfo::index2VirtReg(i));
|
verifyUseList(TargetRegisterInfo::index2VirtReg(i));
|
||||||
for (unsigned i = 1, e = TRI->getNumRegs(); i != e; ++i)
|
for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
|
||||||
verifyUseList(i);
|
verifyUseList(i);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
@ -390,8 +400,8 @@ void MachineRegisterInfo::dumpUses(unsigned Reg) const {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
|
void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
|
||||||
ReservedRegs = TRI->getReservedRegs(MF);
|
ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
|
||||||
assert(ReservedRegs.size() == TRI->getNumRegs() &&
|
assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
|
||||||
"Invalid ReservedRegs vector from target");
|
"Invalid ReservedRegs vector from target");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -401,7 +411,8 @@ bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
|
||||||
|
|
||||||
// Check if any overlapping register is modified, or allocatable so it may be
|
// Check if any overlapping register is modified, or allocatable so it may be
|
||||||
// used later.
|
// used later.
|
||||||
for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
|
for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
|
||||||
|
AI.isValid(); ++AI)
|
||||||
if (!def_empty(*AI) || isAllocatable(*AI))
|
if (!def_empty(*AI) || isAllocatable(*AI))
|
||||||
return false;
|
return false;
|
||||||
return true;
|
return true;
|
||||||
|
|
Loading…
Reference in New Issue