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Add code to emulate LDRH (literal) Arm instruction. 

llvm-svn: 126709
This commit is contained in:
Caroline Tice 2011-02-28 23:15:24 +00:00
parent bbb7e06ad3
commit 6261d240e1
1 changed files with 113 additions and 0 deletions
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113
lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
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@ -6024,6 +6024,117 @@ EmulateInstructionARM::EmulateLDRHImmediate (ARMEncoding encoding)
return true;
}
// LDRH (literal) caculates an address from the PC value and an immediate offset, loads a halfword from memory,
// zero-extends it to form a 32-bit word, and writes it to a register.
bool
EmulateInstructionARM::EmulateLDRHLiteral (ARMEncoding encoding)
{
#if 0
if ConditionPassed() then
EncodingSpecificOperations(); NullCheckIfThumbEE(15);
base = Align(PC,4);
address = if add then (base + imm32) else (base - imm32);
data = MemU[address,2];
if UnalignedSupport() || address<0> = ’0’ then
R[t] = ZeroExtend(data, 32);
else // Can only apply before ARMv7
R[t] = bits(32) UNKNOWN;
#endif
bool success = false;
const uint32_t opcode = OpcodeAsUnsigned (&success);
if (!success)
return false;
if (ConditionPassed())
{
uint32_t t;
uint32_t imm32;
bool add;
// EncodingSpecificOperations(); NullCheckIfThumbEE(15);
switch (encoding)
{
case eEncodingT1:
// if Rt == ’1111’ then SEE "Unallocated memory hints";
// t = UInt(Rt); imm32 = ZeroExtend(imm12, 32); add = (U == ’1’);
t = Bits32 (opcode, 15, 12);
imm32 = Bits32 (opcode, 11, 0);
add = BitIsSet (opcode, 23);
// if t == 13 then UNPREDICTABLE;
if (t == 13)
return false;
break;
case eEncodingA1:
{
uint32_t imm4H = Bits32 (opcode, 11, 8);
uint32_t imm4L = Bits32 (opcode, 3, 0);
// t == UInt(Rt); imm32 = ZeroExtend(imm4H:imm4L, 32); add = (U == ’1’);
t = Bits32 (opcode, 15, 12);
imm32 = (imm4H << 4) & imm4L;
add = BitIsSet (opcode, 23);
// if t == 15 then UNPREDICTABLE;
if (t == 15)
return false;
break;
}
default:
return false;
}
// base = Align(PC,4);
uint64_t pc_value = ReadRegisterUnsigned (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
if (!success)
return false;
addr_t base = AlignPC (pc_value);
addr_t address;
// address = if add then (base + imm32) else (base - imm32);
if (add)
address = base + imm32;
else
address = base - imm32;
// data = MemU[address,2];
Register base_reg;
base_reg.SetRegister (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC);
EmulateInstruction::Context context;
context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset (base_reg, address - base);
uint64_t data = MemURead (context, address, 2, 0, &success);
if (!success)
return false;
// if UnalignedSupport() || address<0> = ’0’ then
if (UnalignedSupport () || BitIsClear (address, 0))
{
// R[t] = ZeroExtend(data, 32);
context.type = eContextRegisterLoad;
context.SetRegisterPlusOffset (base_reg, address - base);
if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + t, data))
return false;
}
else // Can only apply before ARMv7
{
// R[t] = bits(32) UNKNOWN;
WriteBits32Unknown (t);
}
}
return true;
}
// Bitwise Exclusive OR (immediate) performs a bitwise exclusive OR of a register value and an immediate value,
// and writes the result to the destination register. It can optionally update the condition flags based on
// the result.
@ -7396,6 +7507,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
{ 0x0e500010, 0x06100000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt> [<Rn> +/-<Rm> {<shift>}] {!}" },
{ 0x0e5f0000, 0x045f0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>, [...]"},
{ 0xfe500010, 0x06500000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!}" },
{ 0x0e5f00f0, 0x005f00b0, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
//----------------------------------------------------------------------
// Store instructions
@ -7637,6 +7749,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode)
{ 0xfffff800, 0x00008800, ARMV4T_ABOVE, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>, [<Rn>{,#<imm>}]" },
{ 0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c>.w <Rt>,[<Rn>{,#<imm12>}]" },
{ 0xfff00800, 0xf8300800, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateLDRHImmediate, "ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]{!}" },
{ 0xff7f0000, 0xf83f0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>" },
//----------------------------------------------------------------------
// Store instructions