forked from OSchip/llvm-project
[LSR] Add test for multi-edge latch (NFC)
This is additional test coverage for D72519.
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -loop-reduce < %s | FileCheck %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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define void @test(i8* %p.base, i8 %x) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i8 [[X:%.*]], label [[WHILE_END:%.*]] [
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; CHECK-NEXT: i8 10, label [[WHILE_BODY_PREHEADER:%.*]]
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; CHECK-NEXT: i8 20, label [[WHILE_BODY_PREHEADER]]
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; CHECK-NEXT: ]
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; CHECK: while.body.preheader:
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, i8* [[P_BASE:%.*]], i64 1
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; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
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; CHECK: while.body:
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i8* [ [[SCEVGEP1:%.*]], [[WHILE_BODY_BACKEDGE:%.*]] ], [ [[SCEVGEP]], [[WHILE_BODY_PREHEADER]] ]
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; CHECK-NEXT: [[Y:%.*]] = load i8, i8* [[LSR_IV]], align 1
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; CHECK-NEXT: switch i8 [[Y]], label [[WHILE_END_LOOPEXIT:%.*]] [
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; CHECK-NEXT: i8 10, label [[WHILE_BODY_BACKEDGE]]
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; CHECK-NEXT: i8 20, label [[WHILE_BODY_BACKEDGE]]
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; CHECK-NEXT: ]
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; CHECK: while.body.backedge:
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; CHECK-NEXT: [[SCEVGEP1]] = getelementptr i8, i8* [[LSR_IV]], i64 1
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; CHECK-NEXT: br label [[WHILE_BODY]]
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; CHECK: while.end.loopexit:
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; CHECK-NEXT: br label [[WHILE_END]]
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; CHECK: while.end:
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; CHECK-NEXT: ret void
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;
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entry:
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switch i8 %x, label %while.end [
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i8 10, label %while.body
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i8 20, label %while.body
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]
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while.body:
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%p = phi i8* [ %p.inc, %while.body ], [ %p.inc, %while.body ], [ %p.base, %entry ], [ %p.base, %entry ]
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%p.inc = getelementptr inbounds i8, i8* %p, i64 1
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%y = load i8, i8* %p.inc, align 1
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switch i8 %y, label %while.end [
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i8 10, label %while.body
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i8 20, label %while.body
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]
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while.end:
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ret void
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}
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