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Retire TargetRegisterInfo::getSpillAlignment 

getSpillAlign does the same thing.
This commit is contained in:
Benjamin Kramer 2021-05-07 15:15:52 +02:00
parent 13c0316239
commit 6248d11190
4 changed files with 7 additions and 13 deletions
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6
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
View File

@ -281,12 +281,6 @@ public:
return getRegClassInfo(RC).SpillSize / 8;
}
/// Return the minimum required alignment in bytes for a spill slot for
/// a register of this class.
unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
return getRegClassInfo(RC).SpillAlignment / 8;
}
/// Return the minimum required alignment in bytes for a spill slot for
/// a register of this class.
Align getSpillAlign(const TargetRegisterClass &RC) const {

2
llvm/lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -436,7 +436,7 @@ static void assignCalleeSavedSpillSlots(MachineFunction &F,
unsigned Size = RegInfo->getSpillSize(*RC);
if (FixedSlot == FixedSpillSlots + NumFixedSpillSlots) {
// Nope, just spill it anywhere convenient.
Align Alignment(RegInfo->getSpillAlignment(*RC));
Align Alignment = RegInfo->getSpillAlign(*RC);
// We may not be able to satisfy the desired alignment specification of
// the TargetRegisterClass if the stack alignment is smaller. Use the
// min.

2
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -521,7 +521,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
if (NeedsArgAlign && Subtarget.hasV60Ops()) {
LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
Align VecAlign(HRI.getSpillAlignment(Hexagon::HvxVRRegClass));
Align VecAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
MFI.ensureMaxAlignment(LargestAlignSeen);
}

10
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -1022,7 +1022,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
return true;
};
auto UseAligned = [&] (const MachineInstr &MI, unsigned NeedAlign) {
auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) {
if (MI.memoperands().empty())
return false;
return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) {
@ -1086,7 +1086,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
const MachineOperand &BaseOp = MI.getOperand(1);
assert(BaseOp.getSubReg() == 0);
int Offset = MI.getOperand(2).getImm();
unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
: Hexagon::V6_vL32Ub_ai;
BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
@ -1102,7 +1102,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
assert(BaseOp.getSubReg() == 0);
int Offset = MI.getOperand(2).getImm();
unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
: Hexagon::V6_vL32Ub_ai;
BuildMI(MBB, MI, DL, get(NewOpc),
@ -1124,7 +1124,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
const MachineOperand &BaseOp = MI.getOperand(0);
assert(BaseOp.getSubReg() == 0);
int Offset = MI.getOperand(1).getImm();
unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
: Hexagon::V6_vS32Ub_ai;
BuildMI(MBB, MI, DL, get(NewOpc))
@ -1141,7 +1141,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
assert(BaseOp.getSubReg() == 0);
int Offset = MI.getOperand(1).getImm();
unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
: Hexagon::V6_vS32Ub_ai;
BuildMI(MBB, MI, DL, get(NewOpc))