maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86] Support optional NOT stages in the AND(SRL(X,Y),1) -> SETCC(BT(X,Y)) fold 

Extension to D122891, peek through NOT() ops, adjusting the condcode as we go.
This commit is contained in:
Simon Pilgrim 2022-04-04 10:51:26 +01:00
parent 842175676c
commit 623d4b5787
2 changed files with 36 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -47338,9 +47338,24 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
Src.getOpcode() == ISD::TRUNCATE) &&
Src.getOperand(0)->hasOneUse())
Src = Src.getOperand(0);
if (Src.getOpcode() == ISD::SRL && !isa<ConstantSDNode>(Src.getOperand(1)))
if (SDValue BT = getBT(Src.getOperand(0), Src.getOperand(1), dl, DAG))
return DAG.getZExtOrTrunc(getSETCC(X86::COND_B, BT, dl, DAG), dl, VT);
X86::CondCode X86CC = X86::COND_B;
// Peek through AND(NOT(SRL(X,Y)),1).
if (isBitwiseNot(Src)) {
Src = Src.getOperand(0);
X86CC = X86::COND_AE;
}
if (Src.getOpcode() == ISD::SRL &&
!isa<ConstantSDNode>(Src.getOperand(1))) {
SDValue BitNo = Src.getOperand(1);
Src = Src.getOperand(0);
// Peek through AND(SRL(NOT(X),Y),1).
if (isBitwiseNot(Src)) {
Src = Src.getOperand(0);
X86CC = X86CC == X86::COND_AE ? X86::COND_B : X86::COND_AE;
}
if (SDValue BT = getBT(Src, BitNo, dl, DAG))
return DAG.getZExtOrTrunc(getSETCC(X86CC, BT, dl, DAG), dl, VT);
}
}
if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) {

46
llvm/test/CodeGen/X86/setcc.ll
View File

@ -205,21 +205,18 @@ define i64 @t9(i32 %0, i32 %1) {
define i32 @t10(i32 %0, i32 %1) {
; X86-LABEL: t10:
; X86: ## %bb.0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl %cl, %eax
; X86-NEXT: notl %eax
; X86-NEXT: andl $1, %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: btl %edx, %ecx
; X86-NEXT: setae %al
; X86-NEXT: retl
;
; X64-LABEL: t10:
; X64: ## %bb.0:
; X64-NEXT: movl %esi, %ecx
; X64-NEXT: movl %edi, %eax
; X64-NEXT: ## kill: def $cl killed $cl killed $ecx
; X64-NEXT: shrl %cl, %eax
; X64-NEXT: notl %eax
; X64-NEXT: andl $1, %eax
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: btl %esi, %edi
; X64-NEXT: setae %al
; X64-NEXT: retq
%3 = lshr i32 %0, %1
%4 = and i32 %3, 1
@ -231,19 +228,17 @@ define i32 @t11(i32 %0, i32 %1) {
; X86-LABEL: t11:
; X86: ## %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: notl %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: btl %edx, %ecx
; X86-NEXT: setb %al
; X86-NEXT: setae %al
; X86-NEXT: retl
;
; X64-LABEL: t11:
; X64: ## %bb.0:
; X64-NEXT: notl %edi
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: btl %esi, %edi
; X64-NEXT: setb %al
; X64-NEXT: setae %al
; X64-NEXT: retq
%3 = xor i32 %0, -1
%4 = lshr i32 %3, %1
@ -254,23 +249,18 @@ define i32 @t11(i32 %0, i32 %1) {
define i32 @t12(i32 %0, i32 %1) {
; X86-LABEL: t12:
; X86: ## %bb.0:
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: notl %eax
; X86-NEXT: shrl %cl, %eax
; X86-NEXT: notl %eax
; X86-NEXT: andl $1, %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: xorl %eax, %eax
; X86-NEXT: btl %edx, %ecx
; X86-NEXT: setb %al
; X86-NEXT: retl
;
; X64-LABEL: t12:
; X64: ## %bb.0:
; X64-NEXT: movl %esi, %ecx
; X64-NEXT: movl %edi, %eax
; X64-NEXT: notl %eax
; X64-NEXT: ## kill: def $cl killed $cl killed $ecx
; X64-NEXT: shrl %cl, %eax
; X64-NEXT: notl %eax
; X64-NEXT: andl $1, %eax
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: btl %esi, %edi
; X64-NEXT: setb %al
; X64-NEXT: retq
%3 = xor i32 %0, -1
%4 = lshr i32 %3, %1