From 6221be8e461ef5ce6cba05904260f697ce09eb81 Mon Sep 17 00:00:00 2001 From: Zlatko Buljan Date: Thu, 31 Mar 2016 08:51:24 +0000 Subject: [PATCH] [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions Differential Revision: http://reviews.llvm.org/D17334 llvm-svn: 265002 --- .../Mips/Disassembler/MipsDisassembler.cpp | 7 +- .../lib/Target/Mips/MicroMips32r6InstrInfo.td | 66 ++++++++++++++++++- .../lib/Target/Mips/MicroMips64r6InstrInfo.td | 17 +++++ llvm/lib/Target/Mips/MicroMipsInstrFPU.td | 4 +- llvm/lib/Target/Mips/Mips64InstrInfo.td | 3 +- llvm/lib/Target/Mips/MipsInstrFPU.td | 16 +++-- llvm/lib/Target/Mips/MipsInstrInfo.td | 3 +- .../Disassembler/Mips/micromips32r6/valid.txt | 8 +++ .../Disassembler/Mips/micromips64r6/valid.txt | 4 ++ llvm/test/MC/Mips/micromips32r6/invalid.s | 4 ++ llvm/test/MC/Mips/micromips32r6/valid.s | 24 ++++--- llvm/test/MC/Mips/micromips64r6/invalid.s | 14 ++-- llvm/test/MC/Mips/micromips64r6/valid.s | 4 ++ 13 files changed, 145 insertions(+), 29 deletions(-) diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 8f7aeb286d29..81c18683c4a9 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -44,6 +44,7 @@ public: bool hasMips32r6() const { return STI.getFeatureBits()[Mips::FeatureMips32r6]; } + bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; } bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; } @@ -919,9 +920,9 @@ DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, return Result; } - if (hasMips32r6()) { - DEBUG(dbgs() << "Trying MicroMips32r6FPU table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMicroMips32r6FPU32, Instr, Insn, + if (hasMips32r6() && isFP64()) { + DEBUG(dbgs() << "Trying MicroMips32r6FP64 table (32-bit opcodes):\n"); + Result = decodeInstruction(DecoderTableMicroMips32r6FP6432, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index 1c306048903d..b76783a50067 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -65,6 +65,12 @@ class JRCADDIUSP_MMR6_ENC : POOL16C_JRCADDIUSP_FM_MM16R6<0x13>; class LSA_MMR6_ENC : POOL32A_LSA_FM<0b001111>; class LWPC_MMR6_ENC : PCREL19_FM_MMR6<0b01>; class LWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0x2>; +class MFC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfc0", 0b00011, 0b111100>; +class MFC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfc1", 0b10000000>; +class MFC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfc2", 0b0100110100>; +class MFHC0_MMR6_ENC : POOL32A_MFTC0_FM_MMR6<"mfhc0", 0b00011, 0b110100>; +class MFHC1_MMR6_ENC : POOL32F_MFTC1_FM_MMR6<"mfhc1", 0b11000000>; +class MFHC2_MMR6_ENC : POOL32A_MFTC2_FM_MMR6<"mfhc2", 0b1000110100>; class MOD_MMR6_ENC : ARITH_FM_MMR6<"mod", 0x158>; class MODU_MMR6_ENC : ARITH_FM_MMR6<"modu", 0x1d8>; class MUL_MMR6_ENC : ARITH_FM_MMR6<"mul", 0x18>; @@ -617,6 +623,47 @@ class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd, GPR32Opnd HARDFLOAT, FGR_64; class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd>; +class MFC0_MMR6_DESC_BASE { + dag InOperandList = (ins SrcRC:$rs, uimm3:$sel); + dag OutOperandList = (outs DstRC:$rt); + string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel"); + list Pattern = []; + Format f = FrmFR; + string BaseOpcode = opstr; +} +class MFC1_MMR6_DESC_BASE : MipsR6Inst { + dag InOperandList = (ins SrcRC:$fs); + dag OutOperandList = (outs DstRC:$rt); + string AsmString = !strconcat(opstr, "\t$rt, $fs"); + list Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))]; + Format f = FrmFR; + InstrItinClass Itinerary = Itin; + string BaseOpcode = opstr; +} +class MFC2_MMR6_DESC_BASE { + dag InOperandList = (ins SrcRC:$impl); + dag OutOperandList = (outs DstRC:$rt); + string AsmString = !strconcat(opstr, "\t$rt, $impl"); + list Pattern = []; + Format f = FrmFR; + string BaseOpcode = opstr; +} +class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd>; +class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd, + II_MFC1, bitconvert>, HARDFLOAT; +class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd>; +class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd>; +class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd, + II_MFHC1>, HARDFLOAT, FGR_32; +class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd, + II_MFHC1>, HARDFLOAT, FGR_64; +class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>; + /// Floating Point Instructions class FARITH_MMR6_DESC_BASE, ISA_MICROMIPS32R6; +def : MipsInstAlias<"mfc0 $rt, $rs", + (MFC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"mfhc0 $rt, $rs", + (MFHC0_MMR6 GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>, + ISA_MICROMIPS32R6; //===----------------------------------------------------------------------===// // diff --git a/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td index 74e228728b4a..0cc99ac4cb6a 100644 --- a/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td @@ -34,6 +34,9 @@ class DINS_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b001100>; class DMTC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmtc0", 0b01011>; class DMTC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmtc1", 0b10110000>; class DMTC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmtc2", 0b0111110100>; +class DMFC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmfc0", 0b00011>; +class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>; +class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>; //===----------------------------------------------------------------------===// // @@ -106,6 +109,11 @@ class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, bitconvert>; class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd>; +class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd>; +class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd, + II_DMFC1, bitconvert>; +class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd>; + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -144,6 +152,12 @@ let DecoderNamespace = "MicroMipsR6" in { ISA_MICROMIPS64R6; def DMTC2_MM64R6 : StdMMR6Rel, DMTC2_MM64R6_ENC, DMTC2_MM64R6_DESC, ISA_MICROMIPS64R6; + def DMFC0_MM64R6 : StdMMR6Rel, DMFC0_MM64R6_ENC, DMFC0_MM64R6_DESC, + ISA_MICROMIPS64R6; + def DMFC1_MM64R6 : StdMMR6Rel, DMFC1_MM64R6_DESC, DMFC1_MM64R6_ENC, + ISA_MICROMIPS64R6; + def DMFC2_MM64R6 : StdMMR6Rel, DMFC2_MM64R6_ENC, DMFC2_MM64R6_DESC, + ISA_MICROMIPS64R6; } //===----------------------------------------------------------------------===// @@ -151,3 +165,6 @@ let DecoderNamespace = "MicroMipsR6" in { //===----------------------------------------------------------------------===// def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; +def : MipsInstAlias<"dmfc0 $rt, $rd", + (DMFC0_MM64R6 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>, + ISA_MICROMIPS64R6; diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td index a768ef201f8a..3208f2b9f89c 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td @@ -114,8 +114,6 @@ def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, bitconvert>, MFC1_FM_MM<0x80>; def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>; -def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, - MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32; def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, MADDS_FM_MM<0x1>; @@ -147,4 +145,6 @@ let AdditionalPredicates = [InMicroMips] in { fsqrt>, ROUND_W_FM_MM<0, 0x28>; def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32; + def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, + MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32; } diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index fc4d76b518a0..bc7ddd405a4a 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -628,10 +628,11 @@ def : MipsInstAlias<"dsrl $rd, $rt, $rs", ISA_MIPS3; // Two operand (implicit 0 selector) versions: -def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>; let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; + def : MipsInstAlias<"dmfc0 $rt, $rd", + (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>; } def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>; def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>; diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index f9e1679d67bb..8e58272dc6e9 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -367,11 +367,13 @@ def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, bitconvert>, MFC1_FM<0>; def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, bitconvert>, MFC1_FM<4>; -def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, - MFC1_FM<3>, ISA_MIPS32R2, FGR_32; -def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, - MFC1_FM<3>, ISA_MIPS32R2, FGR_64 { - let DecoderNamespace = "Mips64"; +let AdditionalPredicates = [NotInMicroMips] in { + def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, + MFC1_FM<3>, ISA_MIPS32R2, FGR_32; + def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, + MFC1_FM<3>, ISA_MIPS32R2, FGR_64 { + let DecoderNamespace = "Mips64"; + } } let AdditionalPredicates = [NotInMicroMips] in { def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, @@ -381,11 +383,11 @@ let AdditionalPredicates = [NotInMicroMips] in { let DecoderNamespace = "Mips64"; } } -def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, - bitconvert>, MFC1_FM<1>, ISA_MIPS3; let AdditionalPredicates = [NotInMicroMips] in { def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, bitconvert>, MFC1_FM<5>, ISA_MIPS3; + def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, + bitconvert>, MFC1_FM<1>, ISA_MIPS3; } def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index f0780add250b..0302c430aafe 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -1908,10 +1908,11 @@ def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1, MipsIns>, EXT_FM<4>; /// Move Control Registers From/To CPU Registers -def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32; let AdditionalPredicates = [NotInMicroMips] in { def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32; + def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, + ISA_MIPS32; } def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>; def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>; diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt index bf78c046dd14..1802177c7dc0 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -268,3 +268,11 @@ 0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1 0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12 0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14 +0x00 0x67 0x00 0xfc # CHECK: mfc0 $3, $7, 0 +0x00 0x67 0x18 0xfc # CHECK: mfc0 $3, $7, 3 +0x54 0xaa 0x20 0x3b # CHECK: mfc1 $5, $f10 +0x01 0xe5 0x4d 0x3c # CHECK: mfc2 $15, $5 +0x02 0x95 0x00 0xf4 # CHECK: mfhc0 $20, $21, 0 +0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1 +0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6 +0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16 diff --git a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt index 36c33f547d0b..068c3ae04574 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -189,3 +189,7 @@ 0x5a 0x32 0x2a 0xfc # CHECK: dmtc0 $17, $18, 5 0x56 0x74 0x2c 0x3b # CHECK: dmtc1 $19, $f20 0x02 0xb6 0x7d 0x3c # CHECK: dmtc2 $21, $22 +0x5a 0x51 0x00 0xfc # CHECK: dmfc0 $18, $17 +0x59 0x21 0x08 0xfc # CHECK: dmfc0 $9, $1, 1 +0x55 0x24 0x24 0x3b # CHECK: dmfc1 $9, $f4 +0x01 0xd2 0x6d 0x3c # CHECK: dmfc2 $14, $18 diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s index e3142a263a38..78b0cb265b52 100644 --- a/llvm/test/MC/Mips/micromips32r6/invalid.s +++ b/llvm/test/MC/Mips/micromips32r6/invalid.s @@ -114,3 +114,7 @@ mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s index b80f62c9b69a..abcec55afb79 100644 --- a/llvm/test/MC/Mips/micromips32r6/valid.s +++ b/llvm/test/MC/Mips/micromips32r6/valid.s @@ -259,11 +259,19 @@ deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c] tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c] tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c] - mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc] - mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc] - mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b] - mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c] - mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4] - mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4] - mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b] - mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c] + mtc0 $5, $9 # CHECK: mtc0 $5, $9, 0 # encoding: [0x00,0xa9,0x02,0xfc] + mtc0 $1, $2, 7 # CHECK: mtc0 $1, $2, 7 # encoding: [0x00,0x22,0x3a,0xfc] + mtc1 $3, $f4 # CHECK: mtc1 $3, $f4 # encoding: [0x54,0x64,0x28,0x3b] + mtc2 $5, $6 # CHECK: mtc2 $5, $6 # encoding: [0x00,0xa6,0x5d,0x3c] + mthc0 $7, $8 # CHECK: mthc0 $7, $8, 0 # encoding: [0x00,0xe8,0x02,0xf4] + mthc0 $9, $10, 1 # CHECK: mthc0 $9, $10, 1 # encoding: [0x01,0x2a,0x0a,0xf4] + mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b] + mthc2 $13, $14 # CHECK: mthc2 $13, $14 # encoding: [0x01,0xae,0x9d,0x3c] + mfc0 $3, $7 # CHECK: mfc0 $3, $7, 0 # encoding: [0x00,0x67,0x00,0xfc] + mfc0 $3, $7, 3 # CHECK: mfc0 $3, $7, 3 # encoding: [0x00,0x67,0x18,0xfc] + mfc1 $5, $f10 # CHECK: mfc1 $5, $f10 # encoding: [0x54,0xaa,0x20,0x3b] + mfc2 $15, $5 # CHECK: mfc2 $15, $5 # encoding: [0x01,0xe5,0x4d,0x3c] + mfhc0 $20, $21 # CHECK: mfhc0 $20, $21, 0 # encoding: [0x02,0x95,0x00,0xf4] + mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4] + mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b] + mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c] diff --git a/llvm/test/MC/Mips/micromips64r6/invalid.s b/llvm/test/MC/Mips/micromips64r6/invalid.s index 1c92a88e6ef5..09428bd4a716 100644 --- a/llvm/test/MC/Mips/micromips64r6/invalid.s +++ b/llvm/test/MC/Mips/micromips64r6/invalid.s @@ -138,9 +138,11 @@ swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate - mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate - mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate - mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate - dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate - dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate + mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate + dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate + dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate + dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate + dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate diff --git a/llvm/test/MC/Mips/micromips64r6/valid.s b/llvm/test/MC/Mips/micromips64r6/valid.s index 48d2a21b3f62..3412740fbeac 100644 --- a/llvm/test/MC/Mips/micromips64r6/valid.s +++ b/llvm/test/MC/Mips/micromips64r6/valid.s @@ -171,5 +171,9 @@ a: dmtc0 $17, $18, 5 # CHECK: dmtc0 $17, $18, 5 # encoding: [0x5a,0x32,0x2a,0xfc] dmtc1 $19, $f20 # CHECK: dmtc1 $19, $f20 # encoding: [0x56,0x74,0x2c,0x3b] dmtc2 $21, $22 # CHECK: dmtc2 $21, $22 # encoding: [0x02,0xb6,0x7d,0x3c] + dmfc0 $18, $17 # CHECK: dmfc0 $18, $17, 0 # encoding: [0x5a,0x51,0x00,0xfc] + dmfc0 $9, $1, 1 # CHECK: dmfc0 $9, $1, 1 # encoding: [0x59,0x21,0x08,0xfc] + dmfc1 $9, $f4 # CHECK: dmfc1 $9, $f4 # encoding: [0x55,0x24,0x24,0x3b] + dmfc2 $14, $18 # CHECK: dmfc2 $14, $18 # encoding: [0x01,0xd2,0x6d,0x3c] 1: