maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[NFC][regalloc] Use MCRegister appropriately 

Differential Revision: https://reviews.llvm.org/D90506
This commit is contained in:
Mircea Trofin 2020-10-30 15:12:14 -07:00
parent c9d6fe6f7d
commit 61e8a44655
5 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/include/llvm/CodeGen/RegisterScavenging.h
View File

@ -194,10 +194,10 @@ private:
void determineKillsAndDefs(); void determineKillsAndDefs();
/// Add all Reg Units that Reg contains to BV. /// Add all Reg Units that Reg contains to BV.
void addRegUnits(BitVector &BV, Register Reg); void addRegUnits(BitVector &BV, MCRegister Reg);
/// Remove all Reg Units that \p Reg contains from \p BV. /// Remove all Reg Units that \p Reg contains from \p BV.
void removeRegUnits(BitVector &BV, Register Reg); void removeRegUnits(BitVector &BV, MCRegister Reg);
/// Return the candidate register that is unused for the longest after /// Return the candidate register that is unused for the longest after
/// StartMI. UseMI is set to the instruction where the search stopped. /// StartMI. UseMI is set to the instruction where the search stopped.

4
llvm/lib/CodeGen/RegAllocBasic.cpp
View File

@ -119,7 +119,7 @@ public:
// Helper for spilling all live virtual registers currently unified under preg // Helper for spilling all live virtual registers currently unified under preg
// that interfere with the most recently queried lvr. Return true if spilling // that interfere with the most recently queried lvr. Return true if spilling
// was successful, and append any new spilled/split intervals to splitLVRs. // was successful, and append any new spilled/split intervals to splitLVRs.
bool spillInterferences(LiveInterval &VirtReg, Register PhysReg, bool spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
SmallVectorImpl<Register> &SplitVRegs); SmallVectorImpl<Register> &SplitVRegs);
static char ID; static char ID;
@ -206,7 +206,7 @@ void RABasic::releaseMemory() {
// Spill or split all live virtual registers currently unified under PhysReg // Spill or split all live virtual registers currently unified under PhysReg
// that interfere with VirtReg. The newly spilled or split live intervals are // that interfere with VirtReg. The newly spilled or split live intervals are
// returned by appending them to SplitVRegs. // returned by appending them to SplitVRegs.
bool RABasic::spillInterferences(LiveInterval &VirtReg, Register PhysReg, bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
SmallVectorImpl<Register> &SplitVRegs) { SmallVectorImpl<Register> &SplitVRegs) {
// Record each interference and determine if all are spillable before mutating // Record each interference and determine if all are spillable before mutating
// either the union or live intervals. // either the union or live intervals.

4
llvm/lib/CodeGen/RegAllocFast.cpp
View File

@ -495,7 +495,7 @@ void RegAllocFast::reloadAtBegin(MachineBasicBlock &MBB) {
if (PhysReg == 0) if (PhysReg == 0)
continue; continue;
unsigned FirstUnit = *MCRegUnitIterator(PhysReg, TRI); MCRegister FirstUnit = *MCRegUnitIterator(PhysReg, TRI);
if (RegUnitStates[FirstUnit] == regLiveIn) if (RegUnitStates[FirstUnit] == regLiveIn)
continue; continue;
@ -566,7 +566,7 @@ bool RegAllocFast::displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg) {
void RegAllocFast::freePhysReg(MCPhysReg PhysReg) { void RegAllocFast::freePhysReg(MCPhysReg PhysReg) {
LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':'); LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':');
unsigned FirstUnit = *MCRegUnitIterator(PhysReg, TRI); MCRegister FirstUnit = *MCRegUnitIterator(PhysReg, TRI);
switch (unsigned VirtReg = RegUnitStates[FirstUnit]) { switch (unsigned VirtReg = RegUnitStates[FirstUnit]) {
case regFree: case regFree:
LLVM_DEBUG(dbgs() << '\n'); LLVM_DEBUG(dbgs() << '\n');

8
llvm/lib/CodeGen/RegisterScavenging.cpp
View File

@ -97,12 +97,12 @@ void RegScavenger::enterBasicBlockEnd(MachineBasicBlock &MBB) {
} }
} }
void RegScavenger::addRegUnits(BitVector &BV, Register Reg) { void RegScavenger::addRegUnits(BitVector &BV, MCRegister Reg) {
for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
BV.set(*RUI); BV.set(*RUI);
} }
void RegScavenger::removeRegUnits(BitVector &BV, Register Reg) { void RegScavenger::removeRegUnits(BitVector &BV, MCRegister Reg) {
for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
BV.reset(*RUI); BV.reset(*RUI);
} }
@ -134,9 +134,9 @@ void RegScavenger::determineKillsAndDefs() {
} }
if (!MO.isReg()) if (!MO.isReg())
continue; continue;
Register Reg = MO.getReg(); if (!MO.getReg().isPhysical() || isReserved(MO.getReg()))
if (!Register::isPhysicalRegister(Reg) || isReserved(Reg))
continue; continue;
MCRegister Reg = MO.getReg().asMCReg();
if (MO.isUse()) { if (MO.isUse()) {
// Ignore undef uses. // Ignore undef uses.

6
llvm/lib/CodeGen/VirtRegMap.cpp
View File

@ -187,7 +187,7 @@ class VirtRegRewriter : public MachineFunctionPass {
void addLiveInsForSubRanges(const LiveInterval &LI, Register PhysReg) const; void addLiveInsForSubRanges(const LiveInterval &LI, Register PhysReg) const;
void handleIdentityCopy(MachineInstr &MI) const; void handleIdentityCopy(MachineInstr &MI) const;
void expandCopyBundle(MachineInstr &MI) const; void expandCopyBundle(MachineInstr &MI) const;
bool subRegLiveThrough(const MachineInstr &MI, Register SuperPhysReg) const; bool subRegLiveThrough(const MachineInstr &MI, MCRegister SuperPhysReg) const;
public: public:
static char ID; static char ID;
@ -468,7 +468,7 @@ void VirtRegRewriter::expandCopyBundle(MachineInstr &MI) const {
/// \pre \p MI defines a subregister of a virtual register that /// \pre \p MI defines a subregister of a virtual register that
/// has been assigned to \p SuperPhysReg. /// has been assigned to \p SuperPhysReg.
bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI, bool VirtRegRewriter::subRegLiveThrough(const MachineInstr &MI,
Register SuperPhysReg) const { MCRegister SuperPhysReg) const {
SlotIndex MIIndex = LIS->getInstructionIndex(MI); SlotIndex MIIndex = LIS->getInstructionIndex(MI);
SlotIndex BeforeMIUses = MIIndex.getBaseIndex(); SlotIndex BeforeMIUses = MIIndex.getBaseIndex();
SlotIndex AfterMIDefs = MIIndex.getBoundaryIndex(); SlotIndex AfterMIDefs = MIIndex.getBoundaryIndex();
@ -515,7 +515,7 @@ void VirtRegRewriter::rewrite() {
if (!MO.isReg() || !MO.getReg().isVirtual()) if (!MO.isReg() || !MO.getReg().isVirtual())
continue; continue;
Register VirtReg = MO.getReg(); Register VirtReg = MO.getReg();
Register PhysReg = VRM->getPhys(VirtReg); MCRegister PhysReg = VRM->getPhys(VirtReg);
assert(PhysReg != VirtRegMap::NO_PHYS_REG && assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
"Instruction uses unmapped VirtReg"); "Instruction uses unmapped VirtReg");
assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");