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Remove a bunch of unnecessary typecasts to 'const TargetRegisterClass *' 

llvm-svn: 222509
This commit is contained in:
Craig Topper 2014-11-21 05:58:21 +00:00
parent 12e2e726f3
commit 61e88f44f9
7 changed files with 38 additions and 67 deletions
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32
llvm/lib/Target/ARM/ARMFastISel.cpp
View File

@ -586,9 +586,8 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
Reloc::Model RelocM = TM.getRelocationModel();
bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
const TargetRegisterClass *RC = isThumb2 ?
(const TargetRegisterClass*)&ARM::rGPRRegClass :
(const TargetRegisterClass*)&ARM::GPRRegClass;
const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
: &ARM::GPRRegClass;
unsigned DestReg = createResultReg(RC);
// FastISel TLS support on non-MachO is broken, punt to SelectionDAG.
@ -893,9 +892,8 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
// put the alloca address into a register, set the base type back to
// register and continue. This should almost never happen.
if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
const TargetRegisterClass *RC = isThumb2 ?
(const TargetRegisterClass*)&ARM::tGPRRegClass :
(const TargetRegisterClass*)&ARM::GPRRegClass;
const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
: &ARM::GPRRegClass;
unsigned ResultReg = createResultReg(RC);
unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
@ -1094,9 +1092,8 @@ bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
// This is mostly going to be Neon/vector support.
default: return false;
case MVT::i1: {
unsigned Res = createResultReg(isThumb2 ?
(const TargetRegisterClass*)&ARM::tGPRRegClass :
(const TargetRegisterClass*)&ARM::GPRRegClass);
unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass
: &ARM::GPRRegClass);
unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
@ -1500,9 +1497,8 @@ bool ARMFastISel::SelectCmp(const Instruction *I) {
// Now set a register based on the comparison. Explicitly set the predicates
// here.
unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
const TargetRegisterClass *RC = isThumb2 ?
(const TargetRegisterClass*)&ARM::rGPRRegClass :
(const TargetRegisterClass*)&ARM::GPRRegClass;
const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
: &ARM::GPRRegClass;
unsigned DestReg = createResultReg(RC);
Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
unsigned ZeroReg = fastMaterializeConstant(Zero);
@ -2490,15 +2486,9 @@ bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
MFI->setFrameAddressIsTaken(true);
unsigned LdrOpc;
const TargetRegisterClass *RC;
if (isThumb2) {
LdrOpc = ARM::t2LDRi12;
RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
} else {
LdrOpc = ARM::LDRi12;
RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
}
unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
: &ARM::GPRRegClass;
const ARMBaseRegisterInfo *RegInfo =
static_cast<const ARMBaseRegisterInfo *>(

29
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -3129,9 +3129,8 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
else if (RegVT == MVT::v2f64)
RC = &ARM::QPRRegClass;
else if (RegVT == MVT::i32)
RC = AFI->isThumb1OnlyFunction() ?
(const TargetRegisterClass*)&ARM::tGPRRegClass :
(const TargetRegisterClass*)&ARM::GPRRegClass;
RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
: &ARM::GPRRegClass;
else
llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
@ -6515,9 +6514,8 @@ SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
const TargetRegisterClass *TRC = isThumb ?
(const TargetRegisterClass*)&ARM::tGPRRegClass :
(const TargetRegisterClass*)&ARM::GPRRegClass;
const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
: &ARM::GPRRegClass;
// Grab constant pool and fixed stack memory operands.
MachineMemOperand *CPMMO =
@ -6622,9 +6620,8 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
MachineFrameInfo *MFI = MF->getFrameInfo();
int FI = MFI->getFunctionContextIndex();
const TargetRegisterClass *TRC = Subtarget->isThumb() ?
(const TargetRegisterClass*)&ARM::tGPRRegClass :
(const TargetRegisterClass*)&ARM::GPRnopcRegClass;
const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
: &ARM::GPRnopcRegClass;
// Get a mapping of the call site numbers to all of the landing pads they're
// associated with.
@ -7172,13 +7169,10 @@ ARMTargetLowering::EmitStructByval(MachineInstr *MI,
// Select the correct opcode and register class for unit size load/store
bool IsNeon = UnitSize >= 8;
TRC = (IsThumb1 || IsThumb2) ? (const TargetRegisterClass *)&ARM::tGPRRegClass
: (const TargetRegisterClass *)&ARM::GPRRegClass;
TRC = (IsThumb1 || IsThumb2) ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
if (IsNeon)
VecTRC = UnitSize == 16
? (const TargetRegisterClass *)&ARM::DPairRegClass
: UnitSize == 8
? (const TargetRegisterClass *)&ARM::DPRRegClass
VecTRC = UnitSize == 16 ? &ARM::DPairRegClass
: UnitSize == 8 ? &ARM::DPRRegClass
: nullptr;
unsigned BytesLeft = SizeVal % UnitSize;
@ -7627,9 +7621,8 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineRegisterInfo &MRI = Fn->getRegInfo();
// In Thumb mode S must not be specified if source register is the SP or
// PC and if destination register is the SP, so restrict register class
unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
(const TargetRegisterClass*)&ARM::rGPRRegClass :
(const TargetRegisterClass*)&ARM::GPRRegClass);
unsigned NewRsbDstReg =
MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);
// Transfer the remainder of BB and its successor edges to sinkMBB.
SinkBB->splice(SinkBB->begin(), BB,

3
llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
View File

@ -75,8 +75,7 @@ void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
const TargetRegisterClass *RC =
(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
V0 = RegInfo.createVirtualRegister(RC);
V1 = RegInfo.createVirtualRegister(RC);

14
llvm/lib/Target/Mips/MipsMachineFunction.cpp
View File

@ -80,13 +80,10 @@ unsigned MipsFunctionInfo::getGlobalBaseReg() {
const MipsSubtarget &ST = MF.getTarget().getSubtarget<MipsSubtarget>();
const TargetRegisterClass *RC;
if (ST.inMips16Mode())
RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
else
RC = ST.isABI_N64() ?
(const TargetRegisterClass*)&Mips::GPR64RegClass :
(const TargetRegisterClass*)&Mips::GPR32RegClass;
const TargetRegisterClass *RC =
ST.inMips16Mode() ? &Mips::CPU16RegsRegClass
: ST.isABI_N64() ? &Mips::GPR64RegClass
: &Mips::GPR32RegClass;
return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
}
@ -98,8 +95,7 @@ unsigned MipsFunctionInfo::getMips16SPAliasReg() {
if (Mips16SPAliasReg)
return Mips16SPAliasReg;
const TargetRegisterClass *RC;
RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC);
}

5
llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
View File

@ -135,10 +135,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
const TargetRegisterClass *RC;
if (Subtarget->isABI_N64())
RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
else
RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
RC = (Subtarget->isABI_N64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
V0 = RegInfo.createVirtualRegister(RC);
V1 = RegInfo.createVirtualRegister(RC);

15
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -6621,9 +6621,8 @@ PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
MachineRegisterInfo &RegInfo = F->getRegInfo();
unsigned TmpReg = (!BinOpcode) ? incr :
RegInfo.createVirtualRegister(
is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
(const TargetRegisterClass *) &PPC::GPRCRegClass);
RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
: &PPC::GPRCRegClass);
// thisMBB:
// ...
@ -6689,9 +6688,8 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
MachineRegisterInfo &RegInfo = F->getRegInfo();
const TargetRegisterClass *RC =
is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
(const TargetRegisterClass *) &PPC::GPRCRegClass;
const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
: &PPC::GPRCRegClass;
unsigned PtrReg = RegInfo.createVirtualRegister(RC);
unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
@ -7309,9 +7307,8 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
exitMBB->transferSuccessorsAndUpdatePHIs(BB);
MachineRegisterInfo &RegInfo = F->getRegInfo();
const TargetRegisterClass *RC =
is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
(const TargetRegisterClass *) &PPC::GPRCRegClass;
const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
: &PPC::GPRCRegClass;
unsigned PtrReg = RegInfo.createVirtualRegister(RC);
unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
unsigned ShiftReg = RegInfo.createVirtualRegister(RC);

5
llvm/lib/Target/X86/X86FastISel.cpp
View File

@ -2065,9 +2065,8 @@ bool X86FastISel::X86SelectTrunc(const Instruction *I) {
if (!Subtarget->is64Bit()) {
// If we're on x86-32; we can't extract an i8 from a general register.
// First issue a copy to GR16_ABCD or GR32_ABCD.
const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) ?
(const TargetRegisterClass*)&X86::GR16_ABCDRegClass :
(const TargetRegisterClass*)&X86::GR32_ABCDRegClass;
const TargetRegisterClass *CopyRC =
(SrcVT == MVT::i16) ? &X86::GR16_ABCDRegClass : &X86::GR32_ABCDRegClass;
unsigned CopyReg = createResultReg(CopyRC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
CopyReg).addReg(InputReg);