forked from OSchip/llvm-project
[X86][SSE] Added vector sdiv combine tests
llvm-svn: 285112
This commit is contained in:
Simon Pilgrim
parent
ac232ddc23
commit
61cdeb46c9
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; fold (sdiv undef, x) -> 0
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define <4 x i32> @combine_vec_sdiv_undef0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sdiv_undef0:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sdiv_undef0:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = sdiv <4 x i32> undef, %x
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ret <4 x i32> %1
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}
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; fold (sdiv x, undef) -> undef
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define <4 x i32> @combine_vec_sdiv_undef1(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sdiv_undef1:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sdiv_undef1:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = sdiv <4 x i32> %x, undef
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ret <4 x i32> %1
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}
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; fold (sdiv x, 1) -> x
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define <4 x i32> @combine_vec_sdiv_by_one(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sdiv_by_one:
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; SSE: # BB#0:
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sdiv_by_one:
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; AVX: # BB#0:
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; AVX-NEXT: retq
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%1 = sdiv <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %1
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}
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; fold (sdiv x, -1) -> 0 - x
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define <4 x i32> @combine_vec_sdiv_by_negone(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sdiv_by_negone:
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; SSE: # BB#0:
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; SSE-NEXT: pxor %xmm1, %xmm1
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; SSE-NEXT: psubd %xmm0, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sdiv_by_negone:
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; AVX: # BB#0:
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; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = sdiv <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %1
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}
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; fold (sdiv x, y) -> (udiv x, y) iff x and y are positive
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define <4 x i32> @combine_vec_sdiv_by_pos0(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sdiv_by_pos0:
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; SSE: # BB#0:
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: psrld $2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sdiv_by_pos0:
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; AVX: # BB#0:
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpsrld $2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
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%2 = sdiv <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %2
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}
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define <4 x i32> @combine_vec_sdiv_by_pos1(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sdiv_by_pos1:
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; SSE: # BB#0:
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; SSE-NEXT: pand {{.*}}(%rip), %xmm0
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; SSE-NEXT: pextrd $1, %xmm0, %eax
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: sarl $31, %ecx
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; SSE-NEXT: shrl $30, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: sarl $2, %ecx
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; SSE-NEXT: pextrd $2, %xmm0, %eax
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; SSE-NEXT: pextrd $3, %xmm0, %edx
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; SSE-NEXT: pinsrd $1, %ecx, %xmm0
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: sarl $31, %ecx
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; SSE-NEXT: shrl $29, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: sarl $3, %ecx
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; SSE-NEXT: pinsrd $2, %ecx, %xmm0
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; SSE-NEXT: movl %edx, %eax
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; SSE-NEXT: sarl $31, %eax
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; SSE-NEXT: shrl $28, %eax
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; SSE-NEXT: addl %edx, %eax
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; SSE-NEXT: sarl $4, %eax
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; SSE-NEXT: pinsrd $3, %eax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sdiv_by_pos1:
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; AVX: # BB#0:
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; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpextrd $1, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarl $31, %ecx
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; AVX-NEXT: shrl $30, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: sarl $2, %ecx
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; AVX-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm1
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; AVX-NEXT: vpextrd $2, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarl $31, %ecx
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; AVX-NEXT: shrl $29, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: sarl $3, %ecx
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; AVX-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1
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; AVX-NEXT: vpextrd $3, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarl $31, %ecx
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; AVX-NEXT: shrl $28, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: sarl $4, %ecx
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; AVX-NEXT: vpinsrd $3, %ecx, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>
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%2 = sdiv <4 x i32> %1, <i32 1, i32 4, i32 8, i32 16>
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ret <4 x i32> %2
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}
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; fold (sdiv x, (1 << c)) -> x >>u c
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define <4 x i32> @combine_vec_sdiv_by_pow2a(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sdiv_by_pow2a:
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; SSE: # BB#0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $31, %xmm1
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; SSE-NEXT: psrld $30, %xmm1
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; SSE-NEXT: paddd %xmm0, %xmm1
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; SSE-NEXT: psrad $2, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sdiv_by_pow2a:
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; AVX: # BB#0:
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; AVX-NEXT: vpsrad $31, %xmm0, %xmm1
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; AVX-NEXT: vpsrld $30, %xmm1, %xmm1
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; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpsrad $2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = sdiv <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
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ret <4 x i32> %1
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}
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define <4 x i32> @combine_vec_sdiv_by_pow2b(<4 x i32> %x) {
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; SSE-LABEL: combine_vec_sdiv_by_pow2b:
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; SSE: # BB#0:
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; SSE-NEXT: pextrd $1, %xmm0, %eax
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: sarl $31, %ecx
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; SSE-NEXT: shrl $30, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: sarl $2, %ecx
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; SSE-NEXT: pextrd $2, %xmm0, %eax
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; SSE-NEXT: pextrd $3, %xmm0, %edx
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; SSE-NEXT: pinsrd $1, %ecx, %xmm0
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: sarl $31, %ecx
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; SSE-NEXT: shrl $29, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: sarl $3, %ecx
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; SSE-NEXT: pinsrd $2, %ecx, %xmm0
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; SSE-NEXT: movl %edx, %eax
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; SSE-NEXT: sarl $31, %eax
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; SSE-NEXT: shrl $28, %eax
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; SSE-NEXT: addl %edx, %eax
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; SSE-NEXT: sarl $4, %eax
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; SSE-NEXT: pinsrd $3, %eax, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sdiv_by_pow2b:
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; AVX: # BB#0:
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; AVX-NEXT: vpextrd $1, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarl $31, %ecx
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; AVX-NEXT: shrl $30, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: sarl $2, %ecx
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; AVX-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm1
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; AVX-NEXT: vpextrd $2, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarl $31, %ecx
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; AVX-NEXT: shrl $29, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: sarl $3, %ecx
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; AVX-NEXT: vpinsrd $2, %ecx, %xmm1, %xmm1
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; AVX-NEXT: vpextrd $3, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarl $31, %ecx
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; AVX-NEXT: shrl $28, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: sarl $4, %ecx
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; AVX-NEXT: vpinsrd $3, %ecx, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = sdiv <4 x i32> %x, <i32 1, i32 4, i32 8, i32 16>
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ret <4 x i32> %1
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}
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