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Clean up mips16 td file in preparation for massive pseudo lowering work. 

llvm-svn: 175379
This commit is contained in:
Reed Kotler 2013-02-16 23:39:52 +00:00
parent 8df92678a1
commit 61b474f97d
1 changed files with 68 additions and 71 deletions
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139
llvm/lib/Target/Mips/Mips16InstrInfo.td
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@ -64,10 +64,9 @@ class F2RI16_ins<bits<5> _op, string asmstr,
// //
// EXT-CCRR Instruction format // EXT-CCRR Instruction format
// //
class FEXT_CCRXI16_ins<bits<5> _op, string asmstr, class FEXT_CCRXI16_ins<string asmstr>:
InstrItinClass itin>: MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm), !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
!strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> {
let isCodeGenOnly=1; let isCodeGenOnly=1;
} }
@ -113,9 +112,9 @@ class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
// //
// CC-RR Instruction format // CC-RR Instruction format
// //
class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : class FCCRR16_ins<string asmstr> :
FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry), MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> { !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
let isCodeGenOnly=1; let isCodeGenOnly=1;
} }
@ -189,24 +188,22 @@ class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
// //
// EXT-T8I8 // EXT-T8I8
// //
class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2, class FEXT_T8I816_ins<string asmstr, string asmstr2>:
InstrItinClass itin>: MipsPseudo16<(outs),
FEXT_I816<_func, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
(ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm), !strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
!strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t", !strconcat(asmstr, "\t$imm"))),[]> {
!strconcat(asmstr, "\t$imm"))),[], itin> {
let isCodeGenOnly=1; let isCodeGenOnly=1;
} }
// //
// EXT-T8I8I // EXT-T8I8I
// //
class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2, class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
InstrItinClass itin>: MipsPseudo16<(outs),
FEXT_I816<_func, (outs), (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
(ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ), !strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
!strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t", !strconcat(asmstr, "\t$targ"))), []> {
!strconcat(asmstr, "\t$targ"))), [], itin> {
let isCodeGenOnly=1; let isCodeGenOnly=1;
} }
// //
@ -255,9 +252,9 @@ class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
!strconcat(asmstr, "\t$rx, $ry"), [], itin> { !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
} }
class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> : class FRRTR16_ins<string asmstr> :
FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ; !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
// //
// maybe refactor but need a $zero as a dummy first parameter // maybe refactor but need a $zero as a dummy first parameter
@ -332,11 +329,11 @@ class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
// //
// So this pseudo class only has one operand, i.e. op // So this pseudo class only has one operand, i.e. op
// //
class Sel<bits<5> f1, string op, InstrItinClass itin>: class Sel<string op>:
MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
CPU16Regs:$rt), CPU16Regs:$rt),
!strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), [], itin> { !strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
let isCodeGenOnly=1; //let isCodeGenOnly=1;
let Constraints = "$rd = $rd_"; let Constraints = "$rd = $rd_";
} }
@ -355,13 +352,12 @@ class Sel<bits<5> f1, string op, InstrItinClass itin>:
// move $rd, $rs // move $rd, $rs
// //
// //
class SeliT<bits<5> f1, string op1, bits<5> f2, string op2, class SeliT<string op1, string op2>:
InstrItinClass itin>: MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, CPU16Regs:$rl, simm16:$imm),
CPU16Regs:$rl, simm16:$imm), !strconcat(op2,
!strconcat(op2, !strconcat("\t$rl, $imm\n\t",
!strconcat("\t$rl, $imm\n\t", !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin> {
let isCodeGenOnly=1; let isCodeGenOnly=1;
let Constraints = "$rd = $rd_"; let Constraints = "$rd = $rd_";
} }
@ -378,13 +374,13 @@ class SeliT<bits<5> f1, string op1, bits<5> f2, string op2,
// move $rd, $rs // move $rd, $rs
// //
// //
class SelT<bits<5> f1, string op1, bits<5> f2, string op2, class SelT<string op1, string op2>:
InstrItinClass itin>: MipsPseudo16<(outs CPU16Regs:$rd_),
MipsInst16_32<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs, (ins CPU16Regs:$rd, CPU16Regs:$rs,
CPU16Regs:$rl, CPU16Regs:$rr), CPU16Regs:$rl, CPU16Regs:$rr),
!strconcat(op2, !strconcat(op2,
!strconcat("\t$rl, $rr\n\t", !strconcat("\t$rl, $rr\n\t",
!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), [], itin> { !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
let isCodeGenOnly=1; let isCodeGenOnly=1;
let Constraints = "$rd = $rd_"; let Constraints = "$rd = $rd_";
} }
@ -434,6 +430,7 @@ class MayStore {
} }
// //
// Format: ADDIU rx, immediate MIPS16e // Format: ADDIU rx, immediate MIPS16e
// Purpose: Add Immediate Unsigned Word (2-Operand, Extended) // Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
// To add a constant to a 32-bit integer. // To add a constant to a 32-bit integer.
@ -521,18 +518,18 @@ def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
// //
def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16; def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16;
def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16; def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>, def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
cbranch16; cbranch16;
def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16; def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16; def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16; def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>, def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
cbranch16; cbranch16;
// //
@ -542,17 +539,17 @@ def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>,
// //
def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16; def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16;
def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16; def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16; def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16; def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16; def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16; def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>, def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
cbranch16; cbranch16;
// //
@ -847,7 +844,7 @@ def SbRxRyOffMemX16:
// Purpose: if rt==0, do nothing // Purpose: if rt==0, do nothing
// else rs = rt // else rs = rt
// //
def SelBeqZ: Sel<0b00100, "beqz", IIAlu>; def SelBeqZ: Sel<"beqz">;
// //
// Format: SelTBteqZCmp rd, rs, rl, rr // Format: SelTBteqZCmp rd, rs, rl, rr
@ -855,7 +852,7 @@ def SelBeqZ: Sel<0b00100, "beqz", IIAlu>;
// If b==0 then do nothing. // If b==0 then do nothing.
// if b!=0 then rd = rs // if b!=0 then rd = rs
// //
def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>; def SelTBteqZCmp: SelT<"bteqz", "cmp">;
// //
// Format: SelTBteqZCmpi rd, rs, rl, rr // Format: SelTBteqZCmpi rd, rs, rl, rr
@ -863,7 +860,7 @@ def SelTBteqZCmp: SelT<0b000, "bteqz", 0b01010, "cmp", IIAlu>;
// If b==0 then do nothing. // If b==0 then do nothing.
// if b!=0 then rd = rs // if b!=0 then rd = rs
// //
def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>; def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
// //
// Format: SelTBteqZSlt rd, rs, rl, rr // Format: SelTBteqZSlt rd, rs, rl, rr
@ -871,7 +868,7 @@ def SelTBteqZCmpi: SeliT<0b000, "bteqz", 0b01110, "cmpi", IIAlu>;
// If b==0 then do nothing. // If b==0 then do nothing.
// if b!=0 then rd = rs // if b!=0 then rd = rs
// //
def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>; def SelTBteqZSlt: SelT<"bteqz", "slt">;
// //
// Format: SelTBteqZSlti rd, rs, rl, rr // Format: SelTBteqZSlti rd, rs, rl, rr
@ -879,7 +876,7 @@ def SelTBteqZSlt: SelT<0b000, "bteqz", 0b00010, "slt", IIAlu>;
// If b==0 then do nothing. // If b==0 then do nothing.
// if b!=0 then rd = rs // if b!=0 then rd = rs
// //
def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>; def SelTBteqZSlti: SeliT<"bteqz", "slti">;
// //
// Format: SelTBteqZSltu rd, rs, rl, rr // Format: SelTBteqZSltu rd, rs, rl, rr
@ -887,7 +884,7 @@ def SelTBteqZSlti: SeliT<0b000, "bteqz", 0b01010, "slti", IIAlu>;
// If b==0 then do nothing. // If b==0 then do nothing.
// if b!=0 then rd = rs // if b!=0 then rd = rs
// //
def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>; def SelTBteqZSltu: SelT<"bteqz", "sltu">;
// //
// Format: SelTBteqZSltiu rd, rs, rl, rr // Format: SelTBteqZSltiu rd, rs, rl, rr
@ -895,14 +892,14 @@ def SelTBteqZSltu: SelT<0b000, "bteqz", 0b00011, "sltu", IIAlu>;
// If b==0 then do nothing. // If b==0 then do nothing.
// if b!=0 then rd = rs // if b!=0 then rd = rs
// //
def SelTBteqZSltiu: SeliT<0b000, "bteqz", 0b01011, "sltiu", IIAlu>; def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
// //
// Format: SelBnez rd, rs, rt // Format: SelBnez rd, rs, rt
// Purpose: if rt!=0, do nothing // Purpose: if rt!=0, do nothing
// else rs = rt // else rs = rt
// //
def SelBneZ: Sel<0b00101, "bnez", IIAlu>; def SelBneZ: Sel<"bnez">;
// //
// Format: SelTBtneZCmp rd, rs, rl, rr // Format: SelTBtneZCmp rd, rs, rl, rr
@ -910,7 +907,7 @@ def SelBneZ: Sel<0b00101, "bnez", IIAlu>;
// If b!=0 then do nothing. // If b!=0 then do nothing.
// if b0=0 then rd = rs // if b0=0 then rd = rs
// //
def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>; def SelTBtneZCmp: SelT<"btnez", "cmp">;
// //
// Format: SelTBtnezCmpi rd, rs, rl, rr // Format: SelTBtnezCmpi rd, rs, rl, rr
@ -918,7 +915,7 @@ def SelTBtneZCmp: SelT<0b001, "btnez", 0b01010, "cmp", IIAlu>;
// If b!=0 then do nothing. // If b!=0 then do nothing.
// if b==0 then rd = rs // if b==0 then rd = rs
// //
def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>; def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
// //
// Format: SelTBtneZSlt rd, rs, rl, rr // Format: SelTBtneZSlt rd, rs, rl, rr
@ -926,7 +923,7 @@ def SelTBtneZCmpi: SeliT<0b000, "btnez", 0b01110, "cmpi", IIAlu>;
// If b!=0 then do nothing. // If b!=0 then do nothing.
// if b==0 then rd = rs // if b==0 then rd = rs
// //
def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>; def SelTBtneZSlt: SelT<"btnez", "slt">;
// //
// Format: SelTBtneZSlti rd, rs, rl, rr // Format: SelTBtneZSlti rd, rs, rl, rr
@ -934,7 +931,7 @@ def SelTBtneZSlt: SelT<0b001, "btnez", 0b00010, "slt", IIAlu>;
// If b!=0 then do nothing. // If b!=0 then do nothing.
// if b==0 then rd = rs // if b==0 then rd = rs
// //
def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>; def SelTBtneZSlti: SeliT<"btnez", "slti">;
// //
// Format: SelTBtneZSltu rd, rs, rl, rr // Format: SelTBtneZSltu rd, rs, rl, rr
@ -942,7 +939,7 @@ def SelTBtneZSlti: SeliT<0b001, "btnez", 0b01010, "slti", IIAlu>;
// If b!=0 then do nothing. // If b!=0 then do nothing.
// if b==0 then rd = rs // if b==0 then rd = rs
// //
def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>; def SelTBtneZSltu: SelT<"btnez", "sltu">;
// //
// Format: SelTBtneZSltiu rd, rs, rl, rr // Format: SelTBtneZSltiu rd, rs, rl, rr
@ -950,7 +947,7 @@ def SelTBtneZSltu: SelT<0b001, "btnez", 0b00011, "sltu", IIAlu>;
// If b!=0 then do nothing. // If b!=0 then do nothing.
// if b==0 then rd = rs // if b==0 then rd = rs
// //
def SelTBtneZSltiu: SeliT<0b001, "btnez", 0b01011, "sltiu", IIAlu>; def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
// //
// //
// Format: SH ry, offset(rx) MIPS16e // Format: SH ry, offset(rx) MIPS16e
@ -979,14 +976,14 @@ def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
// Purpose: Set on Less Than Immediate (Extended) // Purpose: Set on Less Than Immediate (Extended)
// To record the result of a less-than comparison with a constant. // To record the result of a less-than comparison with a constant.
// //
def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>; def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
// //
// Format: SLTIU rx, immediate MIPS16e // Format: SLTIU rx, immediate MIPS16e
// Purpose: Set on Less Than Immediate Unsigned (Extended) // Purpose: Set on Less Than Immediate Unsigned (Extended)
// To record the result of a less-than comparison with a constant. // To record the result of a less-than comparison with a constant.
// //
def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>; def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
// //
// Format: SLT rx, ry MIPS16e // Format: SLT rx, ry MIPS16e
@ -995,18 +992,18 @@ def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>;
// //
def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>; def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>; def SltCCRxRy16: FCCRR16_ins<"slt">;
// Format: SLTU rx, ry MIPS16e // Format: SLTU rx, ry MIPS16e
// Purpose: Set on Less Than Unsigned // Purpose: Set on Less Than Unsigned
// To record the result of an unsigned less-than comparison. // To record the result of an unsigned less-than comparison.
// //
def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> { def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
let isCodeGenOnly=1; let isCodeGenOnly=1;
} }
def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>; def SltuCCRxRy16: FCCRR16_ins<"sltu">;
// //
// Format: SRAV ry, rx MIPS16e // Format: SRAV ry, rx MIPS16e
// Purpose: Shift Word Right Arithmetic Variable // Purpose: Shift Word Right Arithmetic Variable