forked from OSchip/llvm-project
[AArch64][RegisterBankInfo] Add FPR16 support in value mapping.
NFC. llvm-svn: 317286
This commit is contained in:
Quentin Colombet
parent
a521c4ac55
commit
619d649878
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@ -14,19 +14,21 @@
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namespace llvm {
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RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{
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/* StartIdx, Length, RegBank */
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// 0: FPR 32-bit value.
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// 0: FPR 16-bit value.
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{0, 16, AArch64::FPRRegBank},
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// 1: FPR 32-bit value.
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{0, 32, AArch64::FPRRegBank},
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// 1: FPR 64-bit value.
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// 2: FPR 64-bit value.
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{0, 64, AArch64::FPRRegBank},
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// 2: FPR 128-bit value.
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// 3: FPR 128-bit value.
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{0, 128, AArch64::FPRRegBank},
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// 3: FPR 256-bit value.
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// 4: FPR 256-bit value.
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{0, 256, AArch64::FPRRegBank},
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// 4: FPR 512-bit value.
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// 5: FPR 512-bit value.
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{0, 512, AArch64::FPRRegBank},
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// 5: GPR 32-bit value.
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// 6: GPR 32-bit value.
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{0, 32, AArch64::GPRRegBank},
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// 6: GPR 64-bit value.
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// 7: GPR 64-bit value.
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{0, 64, AArch64::GPRRegBank},
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};
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@ -37,55 +39,62 @@ RegisterBankInfo::ValueMapping AArch64GenRegisterBankInfo::ValMappings[]{
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{nullptr, 0},
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// 3-operands instructions (all binary operations should end up with one of
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// those mapping).
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// 1: FPR 32-bit value. <-- This must match First3OpsIdx.
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// 1: FPR 16-bit value. <-- This must match First3OpsIdx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR16 - PMI_Min], 1},
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// 4: FPR 32-bit value. <-- This must match First3OpsIdx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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// 4: FPR 64-bit value.
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// 7: FPR 64-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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// 7: FPR 128-bit value.
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// 10: FPR 128-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR128 - PMI_Min], 1},
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// 10: FPR 256-bit value.
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// 13: FPR 256-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR256 - PMI_Min], 1},
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// 13: FPR 512-bit value.
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// 16: FPR 512-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR512 - PMI_Min], 1},
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// 16: GPR 32-bit value.
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// 19: GPR 32-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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// 19: GPR 64-bit value. <-- This must match Last3OpsIdx.
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// 22: GPR 64-bit value. <-- This must match Last3OpsIdx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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// Cross register bank copies.
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// 22: FPR 32-bit value to GPR 32-bit value. <-- This must match
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// 25: FPR 16-bit value to GPR 16-bit (invalid). <-- This must match
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// FirstCrossRegCpyIdx.
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{nullptr, 1},
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{nullptr, 1},
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// 27: FPR 32-bit value to GPR 32-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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// 24: FPR 64-bit value to GPR 64-bit value.
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// 29: FPR 64-bit value to GPR 64-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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// 26: FPR 128-bit value to GPR 128-bit value (invalid)
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// 31: FPR 128-bit value to GPR 128-bit value (invalid)
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{nullptr, 1},
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{nullptr, 1},
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// 28: FPR 256-bit value to GPR 256-bit value (invalid)
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// 33: FPR 256-bit value to GPR 256-bit value (invalid)
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{nullptr, 1},
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{nullptr, 1},
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// 30: FPR 512-bit value to GPR 512-bit value (invalid)
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// 35: FPR 512-bit value to GPR 512-bit value (invalid)
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{nullptr, 1},
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{nullptr, 1},
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// 32: GPR 32-bit value to FPR 32-bit value.
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// 37: GPR 32-bit value to FPR 32-bit value.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR32 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR32 - PMI_Min], 1},
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// 34: GPR 64-bit value to FPR 64-bit value. <-- This must match
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// 39: GPR 64-bit value to FPR 64-bit value. <-- This must match
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// LastCrossRegCpyIdx.
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_GPR64 - PMI_Min], 1},
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{&AArch64GenRegisterBankInfo::PartMappings[PMI_FPR64 - PMI_Min], 1},
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@ -145,16 +154,18 @@ unsigned AArch64GenRegisterBankInfo::getRegBankBaseIdxOffset(unsigned RBIdx,
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return -1;
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}
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if (RBIdx == PMI_FirstFPR) {
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if (Size <= 32)
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if (Size <= 16)
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return 0;
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if (Size <= 64)
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if (Size <= 32)
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return 1;
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if (Size <= 128)
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if (Size <= 64)
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return 2;
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if (Size <= 256)
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if (Size <= 128)
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return 3;
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if (Size <= 512)
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if (Size <= 256)
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return 4;
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if (Size <= 512)
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return 5;
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return -1;
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}
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return -1;
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@ -87,9 +87,9 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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assert(checkPartialMappingIdx(PMI_FirstGPR, PMI_LastGPR,
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{PMI_GPR32, PMI_GPR64}) &&
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"PartialMappingIdx's are incorrectly ordered");
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assert(checkPartialMappingIdx(
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PMI_FirstFPR, PMI_LastFPR,
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{PMI_FPR32, PMI_FPR64, PMI_FPR128, PMI_FPR256, PMI_FPR512}) &&
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assert(checkPartialMappingIdx(PMI_FirstFPR, PMI_LastFPR,
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{PMI_FPR16, PMI_FPR32, PMI_FPR64, PMI_FPR128,
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PMI_FPR256, PMI_FPR512}) &&
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"PartialMappingIdx's are incorrectly ordered");
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// Now, the content.
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// Check partial mapping.
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@ -102,6 +102,7 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
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CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
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CHECK_PARTIALMAP(PMI_FPR16, 0, 16, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
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@ -121,6 +122,7 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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CHECK_VALUEMAP(GPR, 32);
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CHECK_VALUEMAP(GPR, 64);
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CHECK_VALUEMAP(FPR, 16);
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CHECK_VALUEMAP(FPR, 32);
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CHECK_VALUEMAP(FPR, 64);
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CHECK_VALUEMAP(FPR, 128);
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@ -25,10 +25,10 @@ class TargetRegisterInfo;
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class AArch64GenRegisterBankInfo : public RegisterBankInfo {
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protected:
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enum PartialMappingIdx {
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PMI_None = -1,
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PMI_FPR32 = 1,
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PMI_FPR16 = 1,
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PMI_FPR32,
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PMI_FPR64,
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PMI_FPR128,
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PMI_FPR256,
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@ -37,7 +37,7 @@ protected:
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PMI_GPR64,
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PMI_FirstGPR = PMI_GPR32,
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PMI_LastGPR = PMI_GPR64,
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PMI_FirstFPR = PMI_FPR32,
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PMI_FirstFPR = PMI_FPR16,
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PMI_LastFPR = PMI_FPR512,
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PMI_Min = PMI_FirstFPR,
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};
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@ -49,10 +49,10 @@ protected:
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enum ValueMappingIdx {
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InvalidIdx = 0,
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First3OpsIdx = 1,
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Last3OpsIdx = 19,
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Last3OpsIdx = 22,
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DistanceBetweenRegBanks = 3,
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FirstCrossRegCpyIdx = 22,
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LastCrossRegCpyIdx = 34,
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FirstCrossRegCpyIdx = 25,
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LastCrossRegCpyIdx = 39,
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DistanceBetweenCrossRegCpy = 2
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};
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