From 61921f779f78182cb0c070d5a6debf378ef6fbd4 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Sun, 29 Oct 2017 20:49:27 +0000
Subject: [PATCH] [X86][SSE] ComputeNumSignBits tests showing missing
 SEXT/AND/XOR/OR demandedelts support

llvm-svn: 316868
---
 .../test/CodeGen/X86/known-signbits-vector.ll | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/llvm/test/CodeGen/X86/known-signbits-vector.ll b/llvm/test/CodeGen/X86/known-signbits-vector.ll
index 0b78017802c2..6ff20b5eba8c 100644
--- a/llvm/test/CodeGen/X86/known-signbits-vector.ll
+++ b/llvm/test/CodeGen/X86/known-signbits-vector.ll
@@ -275,3 +275,71 @@ define <2 x double> @signbits_ashr_concat_ashr_extract_sitofp(<2 x i64> %a0, <4
   %6 = sitofp <2 x i64> %5 to <2 x double>
   ret <2 x double> %6
 }
+
+define float @signbits_ashr_sextinreg_bitops_extract_sitofp(<2 x i64> %a0, <2 x i64> %a1, i32 %a2) nounwind {
+; X32-LABEL: signbits_ashr_sextinreg_bitops_extract_sitofp:
+; X32:       # BB#0:
+; X32-NEXT:    pushl %ebp
+; X32-NEXT:    movl %esp, %ebp
+; X32-NEXT:    andl $-8, %esp
+; X32-NEXT:    subl $16, %esp
+; X32-NEXT:    vmovdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648]
+; X32-NEXT:    vpsrlq $60, %xmm2, %xmm3
+; X32-NEXT:    vpsrlq $61, %xmm2, %xmm2
+; X32-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm3[4,5,6,7]
+; X32-NEXT:    vpsrlq $60, %xmm0, %xmm3
+; X32-NEXT:    vpsrlq $61, %xmm0, %xmm0
+; X32-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
+; X32-NEXT:    vpxor %xmm2, %xmm0, %xmm0
+; X32-NEXT:    vpsubq %xmm2, %xmm0, %xmm0
+; X32-NEXT:    movl 8(%ebp), %eax
+; X32-NEXT:    vpinsrd $0, %eax, %xmm1, %xmm1
+; X32-NEXT:    sarl $31, %eax
+; X32-NEXT:    vpinsrd $1, %eax, %xmm1, %xmm1
+; X32-NEXT:    vpsllq $20, %xmm1, %xmm1
+; X32-NEXT:    vpsrad $20, %xmm1, %xmm2
+; X32-NEXT:    vpsrlq $20, %xmm1, %xmm1
+; X32-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
+; X32-NEXT:    vpand %xmm1, %xmm0, %xmm2
+; X32-NEXT:    vpor %xmm1, %xmm2, %xmm1
+; X32-NEXT:    vpxor %xmm0, %xmm1, %xmm0
+; X32-NEXT:    vmovq %xmm0, {{[0-9]+}}(%esp)
+; X32-NEXT:    fildll {{[0-9]+}}(%esp)
+; X32-NEXT:    fstps {{[0-9]+}}(%esp)
+; X32-NEXT:    flds {{[0-9]+}}(%esp)
+; X32-NEXT:    movl %ebp, %esp
+; X32-NEXT:    popl %ebp
+; X32-NEXT:    retl
+;
+; X64-LABEL: signbits_ashr_sextinreg_bitops_extract_sitofp:
+; X64:       # BB#0:
+; X64-NEXT:    vpsrlq $60, %xmm0, %xmm2
+; X64-NEXT:    vpsrlq $61, %xmm0, %xmm0
+; X64-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
+; X64-NEXT:    vmovdqa {{.*#+}} xmm2 = [4,8]
+; X64-NEXT:    vpxor %xmm2, %xmm0, %xmm0
+; X64-NEXT:    vpsubq %xmm2, %xmm0, %xmm0
+; X64-NEXT:    movslq %edi, %rax
+; X64-NEXT:    vpinsrq $0, %rax, %xmm1, %xmm1
+; X64-NEXT:    vpsllq $20, %xmm1, %xmm1
+; X64-NEXT:    vpsrad $20, %xmm1, %xmm2
+; X64-NEXT:    vpsrlq $20, %xmm1, %xmm1
+; X64-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
+; X64-NEXT:    vpand %xmm1, %xmm0, %xmm2
+; X64-NEXT:    vpor %xmm1, %xmm2, %xmm1
+; X64-NEXT:    vpxor %xmm0, %xmm1, %xmm0
+; X64-NEXT:    vmovq %xmm0, %rax
+; X64-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm0
+; X64-NEXT:    retq
+  %1  = ashr <2 x i64> %a0, <i64 61, i64 60>
+  %2 = sext i32 %a2 to i64
+  %3  = insertelement <2 x i64> %a1, i64 %2, i32 0
+  %4  = shl <2 x i64> %3, <i64 20, i64 20>
+  %5  = ashr <2 x i64> %4, <i64 20, i64 20>
+  %6  = and <2 x i64> %1, %5
+  %7  = or <2 x i64> %6, %5
+  %8  = xor <2 x i64> %7, %1
+  %9  = extractelement <2 x i64> %8, i32 0
+  %10 = sitofp i64 %9 to float
+  ret float %10
+}