forked from OSchip/llvm-project
[AArch64] Basic demand elements for some intrinsics
A lot of neon intrinsics work lane-wise, meaning that non-demanded elements in and not demanded out. This teaches that to AArch64TTIImpl::simplifyDemandedVectorEltsIntrinsic for some simple single-input truncate intrinsics, which can help remove unnecessary instructions. Differential Revision: https://reviews.llvm.org/D117097
This commit is contained in:
David Green
parent
4f19bb6f28
commit
61888d97f6
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@ -1168,6 +1168,32 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
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return None;
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}
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Optional<Value *> AArch64TTIImpl::simplifyDemandedVectorEltsIntrinsic(
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InstCombiner &IC, IntrinsicInst &II, APInt OrigDemandedElts,
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APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
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std::function<void(Instruction *, unsigned, APInt, APInt &)>
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SimplifyAndSetOp) const {
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switch (II.getIntrinsicID()) {
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default:
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break;
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case Intrinsic::aarch64_neon_fcvtxn:
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case Intrinsic::aarch64_neon_rshrn:
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case Intrinsic::aarch64_neon_sqrshrn:
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case Intrinsic::aarch64_neon_sqrshrun:
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case Intrinsic::aarch64_neon_sqshrn:
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case Intrinsic::aarch64_neon_sqshrun:
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case Intrinsic::aarch64_neon_sqxtn:
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case Intrinsic::aarch64_neon_sqxtun:
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case Intrinsic::aarch64_neon_uqrshrn:
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case Intrinsic::aarch64_neon_uqshrn:
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case Intrinsic::aarch64_neon_uqxtn:
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SimplifyAndSetOp(&II, 0, OrigDemandedElts, UndefElts);
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break;
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}
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return None;
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}
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bool AArch64TTIImpl::isWideningInstruction(Type *DstTy, unsigned Opcode,
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ArrayRef<const Value *> Args) {
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@ -106,6 +106,12 @@ public:
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Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
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IntrinsicInst &II) const;
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Optional<Value *> simplifyDemandedVectorEltsIntrinsic(
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InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
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APInt &UndefElts2, APInt &UndefElts3,
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std::function<void(Instruction *, unsigned, APInt, APInt &)>
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SimplifyAndSetOp) const;
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TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
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switch (K) {
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case TargetTransformInfo::RGK_Scalar:
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@ -3,8 +3,7 @@
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define <2 x float> @fcvtxn(<2 x double> %d1) {
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; CHECK-LABEL: @fcvtxn(
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x double> [[D1:%.*]], <2 x double> undef, <2 x i32> zeroinitializer
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; CHECK-NEXT: [[I:%.*]] = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> [[A]])
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; CHECK-NEXT: [[I:%.*]] = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> [[D1:%.*]])
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; CHECK-NEXT: [[S:%.*]] = shufflevector <2 x float> [[I]], <2 x float> undef, <2 x i32> <i32 0, i32 undef>
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; CHECK-NEXT: ret <2 x float> [[S]]
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;
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@ -16,7 +15,7 @@ define <2 x float> @fcvtxn(<2 x double> %d1) {
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define <4 x i16> @rshrn(<2 x i32> %d1, <2 x i32> %d2) {
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; CHECK-LABEL: @rshrn(
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[A]], i32 9)
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: ret <4 x i16> [[S]]
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@ -29,7 +28,7 @@ define <4 x i16> @rshrn(<2 x i32> %d1, <2 x i32> %d2) {
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define <4 x i16> @sqrshrn(<2 x i32> %d1, <2 x i32> %d2) {
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; CHECK-LABEL: @sqrshrn(
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> [[A]], i32 9)
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: ret <4 x i16> [[S]]
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@ -42,7 +41,7 @@ define <4 x i16> @sqrshrn(<2 x i32> %d1, <2 x i32> %d2) {
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define <4 x i16> @sqrshrun(<2 x i32> %d1, <2 x i32> %d2) {
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; CHECK-LABEL: @sqrshrun(
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> [[A]], i32 9)
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: ret <4 x i16> [[S]]
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@ -55,7 +54,7 @@ define <4 x i16> @sqrshrun(<2 x i32> %d1, <2 x i32> %d2) {
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define <4 x i16> @sqshrn(<2 x i32> %d1, <2 x i32> %d2) {
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; CHECK-LABEL: @sqshrn(
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[A]], i32 9)
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: ret <4 x i16> [[S]]
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@ -68,7 +67,7 @@ define <4 x i16> @sqshrn(<2 x i32> %d1, <2 x i32> %d2) {
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define <4 x i16> @sqshrun(<2 x i32> %d1, <2 x i32> %d2) {
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; CHECK-LABEL: @sqshrun(
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> [[A]], i32 9)
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: ret <4 x i16> [[S]]
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@ -81,7 +80,7 @@ define <4 x i16> @sqshrun(<2 x i32> %d1, <2 x i32> %d2) {
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define <4 x i16> @sqxtn(<2 x i32> %d1, <2 x i32> %d2) {
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; CHECK-LABEL: @sqxtn(
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> [[A]])
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: ret <4 x i16> [[S]]
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@ -94,7 +93,7 @@ define <4 x i16> @sqxtn(<2 x i32> %d1, <2 x i32> %d2) {
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define <4 x i16> @sqxtun(<2 x i32> %d1, <2 x i32> %d2) {
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; CHECK-LABEL: @sqxtun(
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> [[A]])
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: ret <4 x i16> [[S]]
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@ -107,7 +106,7 @@ define <4 x i16> @sqxtun(<2 x i32> %d1, <2 x i32> %d2) {
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define <4 x i16> @uqrshrn(<2 x i32> %d1, <2 x i32> %d2) {
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; CHECK-LABEL: @uqrshrn(
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> [[A]], i32 9)
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: ret <4 x i16> [[S]]
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@ -120,7 +119,7 @@ define <4 x i16> @uqrshrn(<2 x i32> %d1, <2 x i32> %d2) {
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define <4 x i16> @uqshrn(<2 x i32> %d1, <2 x i32> %d2) {
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; CHECK-LABEL: @uqshrn(
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[A]], i32 9)
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: ret <4 x i16> [[S]]
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@ -133,7 +132,7 @@ define <4 x i16> @uqshrn(<2 x i32> %d1, <2 x i32> %d2) {
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define <4 x i16> @uqxtn(<2 x i32> %d1, <2 x i32> %d2) {
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; CHECK-LABEL: @uqxtn(
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> [[D2:%.*]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> [[A]])
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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; CHECK-NEXT: ret <4 x i16> [[S]]
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