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Revert r331816 and r331820 - [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64 

Reverting this to see if the clang-cmake-aarch64-global-isel and
clang-cmake-aarch64-quick bots are failing because of this commit.
We know it wasn't r331819.

llvm-svn: 331846
This commit is contained in:
Daniel Sanders 2018-05-09 05:00:17 +00:00
parent 801fca259e
commit 618437459c
12 changed files with 2 additions and 248 deletions
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4
llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
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@ -35,10 +35,6 @@ public:
/// Returns true if MI changed.
bool tryCombineCopy(MachineInstr &MI);
/// If \p MI is extend that consumes the result of a load, try to combine it.
/// Returns true if MI changed.
bool tryCombineExtendingLoads(MachineInstr &MI);
/// Try to transform \p MI by using all of the above
/// combine functions. Returns true if changed.
bool tryCombine(MachineInstr &MI);

34
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
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@ -36,38 +36,6 @@ bool CombinerHelper::tryCombineCopy(MachineInstr &MI) {
return false;
}
bool CombinerHelper::tryCombineExtendingLoads(MachineInstr &MI) {
if (MI.getOpcode() != TargetOpcode::G_ANYEXT &&
MI.getOpcode() != TargetOpcode::G_SEXT &&
MI.getOpcode() != TargetOpcode::G_ZEXT)
return false;
unsigned DstReg = MI.getOperand(0).getReg();
unsigned SrcReg = MI.getOperand(1).getReg();
LLT DstTy = MRI.getType(DstReg);
if (!DstTy.isScalar())
return false;
if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI)) {
unsigned PtrReg = DefMI->getOperand(1).getReg();
MachineMemOperand &MMO = **DefMI->memoperands_begin();
DEBUG(dbgs() << ".. Combine MI: " << MI;);
Builder.setInstr(MI);
Builder.buildLoadInstr(MI.getOpcode() == TargetOpcode::G_SEXT
? TargetOpcode::G_SEXTLOAD
: MI.getOpcode() == TargetOpcode::G_ZEXT
? TargetOpcode::G_ZEXTLOAD
: TargetOpcode::G_LOAD,
DstReg, PtrReg, MMO);
MI.eraseFromParent();
return true;
}
return false;
}
bool CombinerHelper::tryCombine(MachineInstr &MI) {
if (tryCombineCopy(MI))
return true;
return tryCombineExtendingLoads(MI);
return tryCombineCopy(MI);
}

2
llvm/lib/Target/AArch64/AArch64.h
View File

@ -53,7 +53,6 @@ FunctionPass *createAArch64CollectLOHPass();
InstructionSelector *
createAArch64InstructionSelector(const AArch64TargetMachine &,
AArch64Subtarget &, AArch64RegisterBankInfo &);
FunctionPass *createAArch64PreLegalizeCombiner();
void initializeAArch64A53Fix835769Pass(PassRegistry&);
void initializeAArch64A57FPLoadBalancingPass(PassRegistry&);
@ -66,7 +65,6 @@ void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry&);
void initializeAArch64ExpandPseudoPass(PassRegistry&);
void initializeAArch64LoadStoreOptPass(PassRegistry&);
void initializeAArch64SIMDInstrOptPass(PassRegistry&);
void initializeAArch64PreLegalizerCombinerPass(PassRegistry&);
void initializeAArch64PromoteConstantPass(PassRegistry&);
void initializeAArch64RedundantCopyEliminationPass(PassRegistry&);
void initializeAArch64StorePairSuppressPass(PassRegistry&);

104
llvm/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp
View File

@ -1,104 +0,0 @@
//=== lib/CodeGen/GlobalISel/AArch64PreLegalizerCombiner.cpp --------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This pass does combining of machine instructions at the generic MI level,
// before the legalizer.
//
//===----------------------------------------------------------------------===//
#include "AArch64TargetMachine.h"
#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/Support/Debug.h"
#define DEBUG_TYPE "aarch64-prelegalizer-combiner"
using namespace llvm;
using namespace MIPatternMatch;
namespace {
class AArch64PreLegalizerCombinerInfo : public CombinerInfo {
public:
AArch64PreLegalizerCombinerInfo()
: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
/*LegalizerInfo*/ nullptr) {}
virtual bool combine(MachineInstr &MI, MachineIRBuilder &B) const override;
};
bool AArch64PreLegalizerCombinerInfo::combine(MachineInstr &MI,
MachineIRBuilder &B) const {
CombinerHelper Helper(B);
switch (MI.getOpcode()) {
default:
return false;
case TargetOpcode::G_ANYEXT:
case TargetOpcode::G_SEXT:
case TargetOpcode::G_ZEXT:
return Helper.tryCombineExtendingLoads(MI);
}
return false;
}
// Pass boilerplate
// ================
class AArch64PreLegalizerCombiner : public MachineFunctionPass {
public:
static char ID;
AArch64PreLegalizerCombiner();
StringRef getPassName() const override { return "AArch64PreLegalizerCombiner"; }
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override;
};
}
void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<TargetPassConfig>();
MachineFunctionPass::getAnalysisUsage(AU);
}
AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner() : MachineFunctionPass(ID) {
initializeAArch64PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
}
bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
if (MF.getProperties().hasProperty(
MachineFunctionProperties::Property::FailedISel))
return false;
auto *TPC = &getAnalysis<TargetPassConfig>();
AArch64PreLegalizerCombinerInfo PCInfo;
Combiner C(PCInfo, TPC);
return C.combineMachineInstrs(MF);
}
char AArch64PreLegalizerCombiner::ID = 0;
INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE,
"Combine AArch64 machine instrs before legalization",
false, false)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE,
"Combine AArch64 machine instrs before legalization", false,
false)
namespace llvm {
FunctionPass *createAArch64PreLegalizeCombiner() {
return new AArch64PreLegalizerCombiner();
}
} // end namespace llvm

6
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
View File

@ -158,7 +158,6 @@ extern "C" void LLVMInitializeAArch64Target() {
initializeAArch64ExpandPseudoPass(*PR);
initializeAArch64LoadStoreOptPass(*PR);
initializeAArch64SIMDInstrOptPass(*PR);
initializeAArch64PreLegalizerCombinerPass(*PR);
initializeAArch64PromoteConstantPass(*PR);
initializeAArch64RedundantCopyEliminationPass(*PR);
initializeAArch64StorePairSuppressPass(*PR);
@ -339,7 +338,6 @@ public:
bool addPreISel() override;
bool addInstSelector() override;
bool addIRTranslator() override;
void addPreLegalizeMachineIR() override;
bool addLegalizeMachineIR() override;
bool addRegBankSelect() override;
void addPreGlobalInstructionSelect() override;
@ -441,10 +439,6 @@ bool AArch64PassConfig::addIRTranslator() {
return false;
}
void AArch64PassConfig::addPreLegalizeMachineIR() {
addPass(createAArch64PreLegalizeCombiner());
}
bool AArch64PassConfig::addLegalizeMachineIR() {
addPass(new Legalizer());
return false;

1
llvm/lib/Target/AArch64/CMakeLists.txt
View File

@ -43,7 +43,6 @@ add_llvm_target(AArch64CodeGen
AArch64LoadStoreOptimizer.cpp
AArch64MacroFusion.cpp
AArch64MCInstLower.cpp
AArch64PreLegalizerCombiner.cpp
AArch64PromoteConstant.cpp
AArch64PBQPRegAlloc.cpp
AArch64RegisterBankInfo.cpp

2
llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
View File

@ -65,7 +65,7 @@ false:
}
; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(s32) = G_ZEXTLOAD %1:_(p0) :: (load 3 from `i24* undef`, align 1) (in function: odd_type_load)
; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %0:_(s24) = G_LOAD %1:_(p0) :: (load 3 from `i24* undef`, align 1) (in function: odd_type_load)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type_load
; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type_load
define i32 @odd_type_load() {

1
llvm/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
View File

@ -36,7 +36,6 @@
; RUN: -debug-pass=Structure %s -o /dev/null 2>&1 | FileCheck %s --check-prefix DISABLED
; ENABLED: IRTranslator
; ENABLED-NEXT: PreLegalizerCombiner
; ENABLED-NEXT: Legalizer
; ENABLED-NEXT: RegBankSelect
; ENABLED-O0-NEXT: Localizer

25
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extload.mir
View File

@ -1,25 +0,0 @@
# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
define void @test_extload(i8* %addr) {
entry:
ret void
}
...
---
name: test_extload
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_extload
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
; CHECK: $w0 = COPY [[T1]](s32)
%0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
%2:_(s32) = G_ANYEXT %1
$w0 = COPY %2
...

45
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-sextload.mir
View File

@ -1,45 +0,0 @@
# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
define void @test_sextload(i8* %addr) {
entry:
ret void
}
define void @test_sextload_with_copy(i8* %addr) {
entry:
ret void
}
...
---
name: test_sextload
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_sextload
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
; CHECK: $w0 = COPY [[T1]](s32)
%0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
%2:_(s32) = G_SEXT %1
$w0 = COPY %2
...
---
name: test_sextload_with_copy
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_sextload_with_copy
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
; CHECK: $w0 = COPY [[T1]](s32)
%0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
%2:_(s8) = COPY %1
%3:_(s32) = G_SEXT %2
$w0 = COPY %3
...

25
llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-zextload.mir
View File

@ -1,25 +0,0 @@
# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
define void @test_zextload(i8* %addr) {
entry:
ret void
}
...
---
name: test_zextload
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_zextload
; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
; CHECK: $w0 = COPY [[T1]](s32)
%0:_(p0) = COPY $x0
%1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
%2:_(s32) = G_ZEXT %1
$w0 = COPY %2
...

1
llvm/test/CodeGen/AArch64/O0-pipeline.ll
View File

@ -33,7 +33,6 @@
; CHECK-NEXT: Insert stack protectors
; CHECK-NEXT: Module Verifier
; CHECK-NEXT: IRTranslator
; CHECK-NEXT: AArch64PreLegalizerCombiner
; CHECK-NEXT: Legalizer
; CHECK-NEXT: RegBankSelect
; CHECK-NEXT: Localizer