forked from OSchip/llvm-project
AMDGPU: Remove max_scratch_backing_memory_byte_size from kernel header
1. Remove max_scratch_backing_memory_byte_size from kernel header 2. Make it a reserved field 3. Ignore it while parsing assembly for backwards compatibility 4. Bump up minor version of kernel header Differential Revision: https://reviews.llvm.org/D45452 llvm-svn: 329620
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@ -551,14 +551,8 @@ typedef struct amd_kernel_code_s {
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int64_t kernel_code_prefetch_byte_offset;
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uint64_t kernel_code_prefetch_byte_size;
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/// Number of bytes of scratch backing memory required for full
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/// occupancy of target chip. This takes into account the number of
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/// bytes of scratch per work-item, the wavefront size, the maximum
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/// number of wavefronts per CU, and the number of CUs. This is an
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/// upper limit on scratch. If the grid being dispatched is small it
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/// may only need less than this. If the kernel uses no scratch, or
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/// the Finalizer has not computed this value, it must be 0.
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uint64_t max_scratch_backing_memory_byte_size;
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/// Reserved. Must be 0.
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uint64_t reserved0;
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/// Shader program settings for CS. Contains COMPUTE_PGM_RSRC1 and
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/// COMPUTE_PGM_RSRC2 registers.
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@ -2608,6 +2608,13 @@ bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
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bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
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amd_kernel_code_t &Header) {
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// max_scratch_backing_memory_byte_size is deprecated. Ignore it while parsing
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// assembly for backwards compatibility.
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if (ID == "max_scratch_backing_memory_byte_size") {
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Parser.eatToEndOfStatement();
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return false;
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}
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SmallString<40> ErrStr;
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raw_svector_ostream Err(ErrStr);
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if (!parseAmdKernelCodeField(ID, getParser(), Header, Err)) {
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@ -423,7 +423,7 @@ void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
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memset(&Header, 0, sizeof(Header));
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Header.amd_kernel_code_version_major = 1;
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Header.amd_kernel_code_version_minor = 1;
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Header.amd_kernel_code_version_minor = 2;
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Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
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Header.amd_machine_version_major = ISA.Major;
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Header.amd_machine_version_minor = ISA.Minor;
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@ -73,7 +73,6 @@ FIELD2(amd_machine_version_stepping, machine_version_stepping, amd_machine_ve
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FIELD(kernel_code_entry_byte_offset),
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FIELD(kernel_code_prefetch_byte_size),
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FIELD(max_scratch_backing_memory_byte_size),
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COMPPGM1(granulated_workitem_vgpr_count, compute_pgm_rsrc1_vgprs, VGPRS),
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COMPPGM1(granulated_wavefront_sgpr_count, compute_pgm_rsrc1_sgprs, SGPRS),
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@ -65,14 +65,13 @@ amd_kernel_code_t_minimal:
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// ASM-LABEL: {{^}}amd_kernel_code_t_minimal:
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// ASM: .amd_kernel_code_t
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// ASM: amd_code_version_major = 7
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// ASM: amd_code_version_minor = 1
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// ASM: amd_code_version_minor = 2
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// ASM: amd_machine_kind = 1
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// ASM: amd_machine_version_major = 7
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// ASM: amd_machine_version_minor = 0
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// ASM: amd_machine_version_stepping = 0
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// ASM: kernel_code_entry_byte_offset = 256
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// ASM: kernel_code_prefetch_byte_size = 0
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// ASM: max_scratch_backing_memory_byte_size = 0
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// ASM: granulated_workitem_vgpr_count = 1
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// ASM: granulated_wavefront_sgpr_count = 1
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// ASM: priority = 0
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@ -135,7 +135,6 @@ amd_kernel_code_t_test_all:
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// ASM: amd_machine_version_stepping = 5
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// ASM: kernel_code_entry_byte_offset = 512
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// ASM: kernel_code_prefetch_byte_size = 1
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// ASM: max_scratch_backing_memory_byte_size = 1
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// ASM: granulated_workitem_vgpr_count = 1
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// ASM: granulated_wavefront_sgpr_count = 1
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// ASM: priority = 1
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@ -212,14 +211,13 @@ amd_kernel_code_t_minimal:
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// ASM-LABEL: {{^}}amd_kernel_code_t_minimal:
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// ASM: .amd_kernel_code_t
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// ASM: amd_code_version_major = 1
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// ASM: amd_code_version_minor = 1
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// ASM: amd_code_version_minor = 2
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// ASM: amd_machine_kind = 1
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// ASM: amd_machine_version_major = 7
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// ASM: amd_machine_version_minor = 0
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// ASM: amd_machine_version_stepping = 0
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// ASM: kernel_code_entry_byte_offset = 256
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// ASM: kernel_code_prefetch_byte_size = 0
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// ASM: max_scratch_backing_memory_byte_size = 0
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// ASM: granulated_workitem_vgpr_count = 1
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// ASM: granulated_wavefront_sgpr_count = 1
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// ASM: priority = 0
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