forked from OSchip/llvm-project
Convert remaining X-Form and Pseudo instructions over to asm writer
llvm-svn: 16142
This commit is contained in:
Nate Begeman
parent
7063868e2a
commit
6173878304
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@ -102,6 +102,16 @@ namespace {
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MVT::ValueType VT) {
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O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
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}
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void printBranchOperand(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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printOp(MI->getOperand(OpNo));
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}
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void printPICLabel(const MachineInstr *MI, unsigned OpNo,
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MVT::ValueType VT) {
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// FIXME: should probably be converted to cout.width and cout.fill
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O << "\"L0000" << LabelNumber << "$pb\"\n";
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O << "\"L0000" << LabelNumber << "$pb\":";
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}
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void printConstantPool(MachineConstantPool *MCP);
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bool runOnMachineFunction(MachineFunction &F);
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@ -293,42 +303,6 @@ void PPC32AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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assert(((Desc.TSFlags & PPCII::PPC64) == 0) &&
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"Instruction requires 64 bit support");
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// CALLpcrel and CALLindirect are handled specially here to print only the
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// appropriate number of args that the assembler expects. This is because
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// may have many arguments appended to record the uses of registers that are
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// holding arguments to the called function.
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if (Opcode == PPC::COND_BRANCH) {
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std::cerr << "Error: untranslated conditional branch psuedo instruction!\n";
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abort();
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} else if (Opcode == PPC::IMPLICIT_DEF) {
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--EmittedInsts; // Not an actual machine instruction
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O << "; IMPLICIT DEF ";
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printOp(MI->getOperand(0));
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O << "\n";
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return;
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} else if (Opcode == PPC::CALLpcrel) {
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O << TII.getName(Opcode) << " ";
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printOp(MI->getOperand(0));
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O << "\n";
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return;
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} else if (Opcode == PPC::CALLindirect) {
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O << TII.getName(Opcode) << " ";
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printImmOp(MI->getOperand(0), ArgType[0]);
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O << ", ";
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printImmOp(MI->getOperand(1), ArgType[0]);
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O << "\n";
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return;
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} else if (Opcode == PPC::MovePCtoLR) {
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++EmittedInsts; // Actually two machine instructions
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// FIXME: should probably be converted to cout.width and cout.fill
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O << "bl \"L0000" << LabelNumber << "$pb\"\n";
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O << "\"L0000" << LabelNumber << "$pb\":\n";
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O << "\tmflr ";
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printOp(MI->getOperand(0));
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O << "\n";
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return;
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}
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O << TII.getName(Opcode) << " ";
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if (Opcode == PPC::LOADHiAddr) {
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printOp(MI->getOperand(0));
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@ -532,8 +532,8 @@ void ISel::copyGlobalBaseToRegister(MachineBasicBlock *MBB,
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MachineBasicBlock &FirstMBB = F->front();
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MachineBasicBlock::iterator MBBI = FirstMBB.begin();
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GlobalBaseReg = makeAnotherReg(Type::IntTy);
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BuildMI(FirstMBB, MBBI, PPC::IMPLICIT_DEF, 0, PPC::LR);
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BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, GlobalBaseReg);
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BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
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BuildMI(FirstMBB, MBBI, PPC::MFLR, 0, GlobalBaseReg).addReg(PPC::LR);
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GlobalBaseInitialized = true;
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}
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// Emit our copy of GlobalBaseReg to the destination register in the
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@ -41,11 +41,6 @@ namespace {
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// minor pessimization that saves us from having to worry about
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// keeping the offsets up to date later when we emit long branch glue.
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return 12;
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case PPC::MovePCtoLR:
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// MovePCtoLR is actually a combination of a branch-and-link (bl)
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// followed by a move from link register to dest reg (mflr)
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return 8;
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break;
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case PPC::IMPLICIT_DEF: // no asm emitted
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return 0;
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break;
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@ -60,8 +60,8 @@ class I<string name, bits<6> opcode, bit ppc64, bit vmx> : Instruction {
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}
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// 1.7.1 I-Form
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class IForm<string name, bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx>
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: I<name, opcode, ppc64, vmx> {
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class IForm<bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
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field bits<24> LI;
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let ArgCount = 1;
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@ -74,6 +74,8 @@ class IForm<string name, bits<6> opcode, bit aa, bit lk, bit ppc64, bit vmx>
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let Inst{6-29} = LI;
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let Inst{30} = aa;
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let Inst{31} = lk;
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let OperandList = OL;
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let AsmString = asmstr;
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}
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// 1.7.2 B-Form
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@ -311,8 +313,8 @@ class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
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let B = 0;
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}
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class XForm_16<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: I<name, opcode, ppc64, vmx> {
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class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
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field bits<3> BF;
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field bits<1> L;
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field bits<5> RA;
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@ -332,10 +334,17 @@ class XForm_16<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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let Inst{16-20} = RB;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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let OperandList = OL;
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let AsmString = asmstr;
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}
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class XForm_16_ext<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx>
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: XForm_16<name, opcode, xo, ppc64, vmx> {
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class XForm_16_ext<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XForm_16<opcode, xo, ppc64, vmx, OL, asmstr> {
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let ArgCount = 3;
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let Arg1Type = Gpr.Value;
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let Arg2Type = Gpr.Value;
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let Arg3Type = 0;
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let L = ppc64;
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}
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@ -395,8 +404,8 @@ class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
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let Arg2Type = Imm5.Value;
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}
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class XLForm_2<string name, bits<6> opcode, bits<10> xo, bit lk, bit ppc64,
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bit vmx> : I<name, opcode, ppc64, vmx> {
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class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,
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dag OL, string asmstr> : I<"", opcode, ppc64, vmx> {
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field bits<5> BO;
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field bits<5> BI;
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field bits<2> BH;
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@ -414,11 +423,14 @@ class XLForm_2<string name, bits<6> opcode, bits<10> xo, bit lk, bit ppc64,
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let Inst{19-20} = BH;
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let Inst{21-30} = xo;
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let Inst{31} = lk;
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let OperandList = OL;
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let AsmString = asmstr;
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}
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class XLForm_2_ext<string name, bits<6> opcode, bits<10> xo, bits<5> bo,
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bits<5> bi, bit lk, bit ppc64, bit vmx>
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: XLForm_2<name, opcode, xo, lk, ppc64, vmx> {
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class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
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bits<5> bi, bit lk, bit ppc64, bit vmx,
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dag OL, string asmstr>
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: XLForm_2<opcode, xo, lk, ppc64, vmx, OL, asmstr> {
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let ArgCount = 0;
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let Arg0Type = 0;
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let Arg1Type = 0;
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@ -634,17 +646,18 @@ class MDForm_1<bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx,
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//===----------------------------------------------------------------------===//
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class Pseudo<string name> : I<name, 0, 0, 0> {
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let Name = name;
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let ArgCount = 0;
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let PPC64 = 0;
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let VMX = 0;
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class Pseudo<dag OL, string asmstr> : I<"", 0, 0, 0> {
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let ArgCount = 0;
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let PPC64 = 0;
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let VMX = 0;
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let Arg0Type = Pseudo.Value;
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let Arg1Type = Pseudo.Value;
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let Arg2Type = Pseudo.Value;
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let Arg3Type = Pseudo.Value;
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let Arg4Type = 0;
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let Arg0Type = Pseudo.Value;
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let Arg1Type = Pseudo.Value;
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let Arg2Type = Pseudo.Value;
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let Arg3Type = Pseudo.Value;
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let Arg4Type = 0;
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let Inst{31-0} = 0;
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let Inst{31-0} = 0;
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let OperandList = OL;
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let AsmString = asmstr;
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}
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@ -15,7 +15,7 @@
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include "PowerPCInstrFormats.td"
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let isTerminator = 1, isReturn = 1 in
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def BLR : XLForm_2_ext<"blr", 19, 16, 20, 31, 1, 0, 0>;
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def BLR : XLForm_2_ext<19, 16, 20, 31, 1, 0, 0, (ops), "blr">;
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def u5imm : Operand<i8> {
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let PrintMethod = "printU5ImmOperand";
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@ -26,18 +26,23 @@ def u6imm : Operand<i8> {
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def u16imm : Operand<i16> {
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let PrintMethod = "printU16ImmOperand";
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}
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def target : Operand<i32> {
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let PrintMethod = "printBranchOperand";
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}
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def piclabel: Operand<i32> {
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let PrintMethod = "printPICLabel";
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}
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// Pseudo-instructions:
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def PHI : Pseudo<"PHI">;
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def ADJCALLSTACKDOWN : Pseudo<"ADJCALLSTACKDOWN">;
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def ADJCALLSTACKUP : Pseudo<"ADJCALLSTACKUP">;
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let Defs = [LR] in
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def MovePCtoLR : Pseudo<"MovePCtoLR">;
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def IMPLICIT_DEF : Pseudo<"IMPLICIT_DEF">;
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def PHI : Pseudo<(ops), "; PHI">;
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def ADJCALLSTACKDOWN : Pseudo<(ops), "; ADJCALLSTACKDOWN">;
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def ADJCALLSTACKUP : Pseudo<(ops), "; ADJCALLSTACKUP">;
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def IMPLICIT_DEF : Pseudo<(ops), "; IMPLICIT_DEF">;
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def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
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let isBranch = 1, isTerminator = 1 in {
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def COND_BRANCH : Pseudo<"COND_BRANCH">;
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def B : IForm<"b", 18, 0, 0, 0, 0>;
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def COND_BRANCH : Pseudo<(ops), "; COND_BRANCH">;
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def B : IForm<18, 0, 0, 0, 0, (ops target:$func), "b $func">;
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// FIXME: 4*CR# needs to be added to the BI field!
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// This will only work for CR0 as it stands now
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def BLT : BForm_ext<"blt", 16, 0, 0, 12, 0, 0, 0>;
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@ -55,8 +60,8 @@ let isBranch = 1, isTerminator = 1, isCall = 1,
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LR,XER,CTR,
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CR0,CR1,CR5,CR6,CR7] in {
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// Convenient aliases for call instructions
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def CALLpcrel : IForm<"bl", 18, 0, 1, 0, 0>;
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def CALLindirect : XLForm_2_ext<"bctrl", 19, 528, 20, 31, 1, 0, 0>;
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def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
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def CALLindirect : XLForm_2_ext<19, 528, 20, 31, 1, 0, 0, (ops), "bctrl">;
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}
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def LA : DForm_2<"la", 14, 0, 0>;
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@ -96,13 +101,6 @@ def LD : DSForm_2<"ld", 58, 0, 1, 0>;
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def STD : DSForm_2<"std", 62, 0, 1, 0>;
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def STDU : DSForm_2<"stdu", 62, 1, 1, 0>;
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def CMP : XForm_16<"cmp", 31, 0, 0, 0>;
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def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>;
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def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>;
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def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>;
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def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>;
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def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>;
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// D-Form instructions. Most instructions that perform an operation on a
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// register and an immediate are of this type.
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//
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@ -200,6 +198,24 @@ def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
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"extsh $rA, $rS">;
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def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
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"extsw $rA, $rS">;
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def CMP : XForm_16<31, 0, 0, 0,
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(ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
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"cmp $crD, $long, $rA, $rB">;
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def CMPL : XForm_16<31, 32, 0, 0,
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(ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
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"cmpl $crD, $long, $rA, $rB">;
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def CMPW : XForm_16_ext<31, 0, 0, 0,
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(ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
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"cmpw $crD, $rA, $rB">;
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def CMPD : XForm_16_ext<31, 0, 1, 0,
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(ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
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"cmpd $crD, $rA, $rB">;
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def CMPLW : XForm_16_ext<31, 32, 0, 0,
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(ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
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"cmplw $crD, $rA, $rB">;
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def CMPLD : XForm_16_ext<31, 32, 1, 0,
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(ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
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"cmpld $crD, $rA, $rB">;
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def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
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"fcmpu $crD, $fA, $fB">;
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def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
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