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This patch adds support for 16 bit floating point registers to the inline asm register selection on AArch64. 

Without this patch, register allocation for the example below fails.

define half @test(half %a1, half %a2) #0 {
entry:
  %0 = tail call half asm "sqrshl ${0:h}, ${1:h}, ${2:h}", "=w,w,w" (half %a1, half %a2) #1
  ret half %0
}

Patch by Florian Hahn.

Differential Revision: https://reviews.llvm.org/D25080

llvm-svn: 286111
This commit is contained in:
Amara Emerson 2016-11-07 15:42:12 +00:00
parent d6daac4746
commit 614b44bbe9
2 changed files with 22 additions and 0 deletions
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2
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -4780,6 +4780,8 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
return std::make_pair(0U, &AArch64::GPR64commonRegClass);
return std::make_pair(0U, &AArch64::GPR32commonRegClass);
case 'w':
if (VT.getSizeInBits() == 16)
return std::make_pair(0U, &AArch64::FPR16RegClass);
if (VT.getSizeInBits() == 32)
return std::make_pair(0U, &AArch64::FPR32RegClass);
if (VT.getSizeInBits() == 64)

20
llvm/test/CodeGen/AArch64/neon-inline-asm-16-bit-fp.ll Normal file
View File

@ -0,0 +1,20 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
; generated from
; __fp16 test(__fp16 a1, __fp16 a2) {
; __fp16 res0;
; __asm__("sqrshl %h[__res], %h[__A], %h[__B]"
; : [__res] "=w" (res0)
; : [__A] "w" (a1), [__B] "w" (a2)
; :
; );
; return res0;
;}
; Function Attrs: nounwind readnone
define half @test(half %a1, half %a2) #0 {
entry:
;CHECK: sqrshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
%0 = tail call half asm "sqrshl ${0:h}, ${1:h}, ${2:h}", "=w,w,w" (half %a1, half %a2) #1
ret half %0
}