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AMDGPU/InsertWaitcnts: Cleanup some old cruft (NFCI) 

Summary: Remove redundant logic and simplify control flow.

Reviewers: msearles, rampitec, scott.linder, kanarayan

Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D54086

llvm-svn: 346363
This commit is contained in:
Nicolai Haehnle 2018-11-07 21:53:36 +00:00
parent 0ab31c9c44
commit 61396ff67c
1 changed files with 69 additions and 89 deletions
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36
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
View File

@ -880,24 +880,14 @@ void SIInsertWaitcnts::generateWaitcntInstBefore(
// Start with an assumption that there is no need to emit.
unsigned int EmitWaitcnt = 0;
// No need to wait before phi. If a phi-move exists, then the wait should
// has been inserted before the move. If a phi-move does not exist, then
// wait should be inserted before the real use. The same is true for
// sc-merge. It is not a coincident that all these cases correspond to the
// instructions that are skipped in the assembling loop.
bool NeedLineMapping = false; // TODO: Check on this.
// ForceEmitZeroWaitcnt: force a single s_waitcnt 0 due to hw bug
bool ForceEmitZeroWaitcnt = false;
setForceEmitWaitcnt();
bool IsForceEmitWaitcnt = isForceEmitWaitcnt();
if (MI.isDebugInstr() &&
// TODO: any other opcode?
!NeedLineMapping) {
if (MI.isDebugInstr())
return;
}
// See if an s_waitcnt is forced at block entry, or is needed at
// program end.
@ -1141,7 +1131,6 @@ void SIInsertWaitcnts::generateWaitcntInstBefore(
if (EmitWaitcnt || IsForceEmitWaitcnt) {
int CntVal[NUM_INST_CNTS];
bool UseDefaultWaitcntStrategy = true;
if (ForceEmitZeroWaitcnt || ForceEmitZeroWaitcnts) {
// Force all waitcnts to 0.
for (enum InstCounterType T = VM_CNT; T < NUM_INST_CNTS;
@ -1151,10 +1140,7 @@ void SIInsertWaitcnts::generateWaitcntInstBefore(
CntVal[VM_CNT] = 0;
CntVal[EXP_CNT] = 0;
CntVal[LGKM_CNT] = 0;
UseDefaultWaitcntStrategy = false;
}
if (UseDefaultWaitcntStrategy) {
} else {
for (enum InstCounterType T = VM_CNT; T < NUM_INST_CNTS;
T = (enum InstCounterType)(T + 1)) {
if (EmitWaitcnt & CNT_MASK(T)) {
@ -1178,8 +1164,6 @@ void SIInsertWaitcnts::generateWaitcntInstBefore(
}
}
// If we are not waiting on any counter we can skip the wait altogether.
if (EmitWaitcnt != 0 || IsForceEmitWaitcnt) {
MachineInstr *OldWaitcnt = ScoreBrackets->getWaitcnt();
int Imm = (!OldWaitcnt) ? 0 : OldWaitcnt->getOperand(0).getImm();
if (!OldWaitcnt ||
@ -1192,8 +1176,7 @@ void SIInsertWaitcnts::generateWaitcntInstBefore(
MachineLoop *ContainingLoop = MLI->getLoopFor(MI.getParent());
if (ContainingLoop) {
MachineBasicBlock *TBB = ContainingLoop->getHeader();
BlockWaitcntBrackets *ScoreBracket =
BlockWaitcntBracketsMap[TBB].get();
BlockWaitcntBrackets *ScoreBracket = BlockWaitcntBracketsMap[TBB].get();
if (!ScoreBracket) {
assert(!BlockVisitedSet.count(TBB));
BlockWaitcntBracketsMap[TBB] =
@ -1201,8 +1184,7 @@ void SIInsertWaitcnts::generateWaitcntInstBefore(
ScoreBracket = BlockWaitcntBracketsMap[TBB].get();
}
ScoreBracket->setRevisitLoop(true);
LLVM_DEBUG(dbgs()
<< "set-revisit2: Block"
LLVM_DEBUG(dbgs() << "set-revisit2: Block"
<< ContainingLoop->getHeader()->getNumber() << '\n';);
}
}
@ -1236,14 +1218,13 @@ void SIInsertWaitcnts::generateWaitcntInstBefore(
break;
}
if (insertSWaitInst) {
if (OldWaitcnt && OldWaitcnt->getOpcode() == AMDGPU::S_WAITCNT) {
if (OldWaitcnt) {
assert(OldWaitcnt->getOpcode() == AMDGPU::S_WAITCNT);
if (ForceEmitZeroWaitcnts)
LLVM_DEBUG(
dbgs()
LLVM_DEBUG(dbgs()
<< "Force emit s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)\n");
if (IsForceEmitWaitcnt)
LLVM_DEBUG(dbgs()
<< "Force emit a s_waitcnt due to debug counter\n");
LLVM_DEBUG(dbgs() << "Force emit a s_waitcnt due to debug counter\n");
OldWaitcnt->getOperand(0).setImm(Enc);
if (!OldWaitcnt->getParent())
@ -1269,7 +1250,6 @@ void SIInsertWaitcnts::generateWaitcntInstBefore(
}
}
}
}
void SIInsertWaitcnts::insertWaitcntBeforeCF(MachineBasicBlock &MBB,
MachineInstr *Waitcnt) {