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[mips] Avoid redundant sign extension of the result of binary bitwise instructions. 

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7581

llvm-svn: 229675
This commit is contained in:
Vasileios Kalintiris 2015-02-18 14:57:05 +00:00
parent 335c29ed0b
commit 611cb70b83
4 changed files with 11 additions and 13 deletions
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8
llvm/lib/Target/Mips/Mips64InstrInfo.td
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@ -486,6 +486,14 @@ def : MipsPat<(trunc (assertzext GPR64:$src)),
def : MipsPat<(i32 (trunc GPR64:$src)),
(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
// Bypass trunc nodes for bitwise ops.
def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
// 32-to-64-bit extension
def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;

5
llvm/test/CodeGen/Mips/llvm-ir/and.ll
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@ -51,10 +51,7 @@ define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: and_i32:
; GP32: and $2, $4, $5
; GP64: and $[[T0:[0-9]+]], $4, $5
; GP64: sll $2, $[[T0]], 0
; ALL: and $2, $4, $5
%r = and i32 %a, %b
ret i32 %r

6
llvm/test/CodeGen/Mips/llvm-ir/or.ll
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@ -51,11 +51,7 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: or_i32:
; GP32: or $2, $4, $5
; GP64: or $[[T0:[0-9]+]], $4, $5
; FIXME: The sll instruction below is redundant.
; GP64: sll $2, $[[T0]], 0
; ALL: or $2, $4, $5
%r = or i32 %a, %b
ret i32 %r

5
llvm/test/CodeGen/Mips/llvm-ir/xor.ll
View File

@ -51,10 +51,7 @@ define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: xor_i32:
; GP32: xor $2, $4, $5
; GP64: xor $[[T0:[0-9]+]], $4, $5
; GP64: sll $2, $[[T0]], 0
; ALL: xor $2, $4, $5
%r = xor i32 %a, %b
ret i32 %r