forked from OSchip/llvm-project
[AVX] When joining two XMM registers into a YMM register, make sure that the
lower XMM register gets in first. This will allow the SUBREG pattern to elliminate the first vector insertion. llvm-svn: 137310
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@ -213,6 +213,7 @@ namespace {
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SDValue visitLOAD(SDNode *N);
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SDValue visitSTORE(SDNode *N);
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SDValue visitINSERT_VECTOR_ELT(SDNode *N);
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SDValue visitINSERT_SUBVECTOR(SDNode *N);
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SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
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SDValue visitBUILD_VECTOR(SDNode *N);
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SDValue visitCONCAT_VECTORS(SDNode *N);
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@ -1102,6 +1103,7 @@ SDValue DAGCombiner::visit(SDNode *N) {
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case ISD::LOAD: return visitLOAD(N);
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case ISD::STORE: return visitSTORE(N);
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case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
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case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
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case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
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case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
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case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
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@ -7136,6 +7138,36 @@ SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
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}
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}
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SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode* N) {
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DebugLoc dl = N->getDebugLoc();
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EVT VT = N->getValueType(0);
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// When inserting a subvector into a vector, make sure to start
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// inserting starting the Zero index. This will allow making the
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// first insertion using a subreg insertion, and save a register.
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SDValue V = N->getOperand(0);
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if (V->getOpcode() == ISD::INSERT_SUBVECTOR && V->hasOneUse()) {
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ConstantSDNode *N_Idx = dyn_cast<ConstantSDNode>(N->getOperand(2));
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ConstantSDNode *V_Idx = dyn_cast<ConstantSDNode>(V->getOperand(2));
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uint64_t Nc = N_Idx->getZExtValue();
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uint64_t Vc = V_Idx->getZExtValue();
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// Reorder insertion to vector
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if (Nc < Vc) {
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SDValue NewV = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT,
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V->getOperand(0),
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N->getOperand(1),
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N->getOperand(2));
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return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT,
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NewV,
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V->getOperand(1),
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V->getOperand(2));
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}
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}
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return SDValue();
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}
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/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
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/// an AND to a vector_shuffle with the destination vector and a zero vector.
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/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
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