forked from OSchip/llvm-project
Enabling 3DNow! prefetch instruction support for a few AMD processors in the
clang front end. This change will allow the __PRFCHW__ macro to be set on these processors and hence include prfchwintrin.h in x86intrin.h header. Support for the intrinsic itself seems to have already been added in r178041. Differential Revision: http://llvm-reviews.chandlerc.com/D1934 llvm-svn: 192829
This commit is contained in:
Yunzhong Gao
parent
dfc277f350
commit
6108936fa6
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@ -2120,6 +2120,7 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
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setFeatureEnabledImpl(Features, "cx16", true);
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setFeatureEnabledImpl(Features, "lzcnt", true);
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setFeatureEnabledImpl(Features, "popcnt", true);
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setFeatureEnabledImpl(Features, "prfchw", true);
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break;
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case CK_BTVER2:
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setFeatureEnabledImpl(Features, "avx", true);
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@ -2127,6 +2128,7 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
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setFeatureEnabledImpl(Features, "lzcnt", true);
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setFeatureEnabledImpl(Features, "aes", true);
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setFeatureEnabledImpl(Features, "pclmul", true);
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setFeatureEnabledImpl(Features, "prfchw", true);
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setFeatureEnabledImpl(Features, "bmi", true);
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setFeatureEnabledImpl(Features, "f16c", true);
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setFeatureEnabledImpl(Features, "cx16", true);
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@ -2136,6 +2138,7 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
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setFeatureEnabledImpl(Features, "lzcnt", true);
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setFeatureEnabledImpl(Features, "aes", true);
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setFeatureEnabledImpl(Features, "pclmul", true);
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setFeatureEnabledImpl(Features, "prfchw", true);
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setFeatureEnabledImpl(Features, "cx16", true);
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break;
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case CK_BDVER2:
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@ -2143,6 +2146,7 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
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setFeatureEnabledImpl(Features, "lzcnt", true);
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setFeatureEnabledImpl(Features, "aes", true);
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setFeatureEnabledImpl(Features, "pclmul", true);
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setFeatureEnabledImpl(Features, "prfchw", true);
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setFeatureEnabledImpl(Features, "bmi", true);
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setFeatureEnabledImpl(Features, "fma", true);
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setFeatureEnabledImpl(Features, "f16c", true);
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@ -2467,6 +2471,13 @@ bool X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features,
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Features.push_back("+popcnt");
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}
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// Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
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if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
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std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
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HasPRFCHW = true;
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Features.push_back("+prfchw");
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}
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// LLVM doesn't have a separate switch for fpmath, so only accept it if it
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// matches the selected sse level.
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if (FPMath == FP_SSE && SSELevel < SSE1) {
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@ -1166,6 +1166,7 @@
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// CHECK_BTVER1_M32: #define __LZCNT__ 1
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// CHECK_BTVER1_M32: #define __MMX__ 1
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// CHECK_BTVER1_M32: #define __POPCNT__ 1
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// CHECK_BTVER1_M32: #define __PRFCHW__ 1
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// CHECK_BTVER1_M32: #define __SSE2_MATH__ 1
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// CHECK_BTVER1_M32: #define __SSE2__ 1
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// CHECK_BTVER1_M32: #define __SSE3__ 1
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@ -1186,6 +1187,7 @@
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// CHECK_BTVER1_M64: #define __LZCNT__ 1
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// CHECK_BTVER1_M64: #define __MMX__ 1
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// CHECK_BTVER1_M64: #define __POPCNT__ 1
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// CHECK_BTVER1_M64: #define __PRFCHW__ 1
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// CHECK_BTVER1_M64: #define __SSE2_MATH__ 1
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// CHECK_BTVER1_M64: #define __SSE2__ 1
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// CHECK_BTVER1_M64: #define __SSE3__ 1
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@ -1210,6 +1212,7 @@
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// CHECK_BTVER2_M32: #define __LZCNT__ 1
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// CHECK_BTVER2_M32: #define __MMX__ 1
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// CHECK_BTVER2_M32: #define __POPCNT__ 1
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// CHECK_BTVER2_M32: #define __PRFCHW__ 1
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// CHECK_BTVER2_M32: #define __SSE2_MATH__ 1
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// CHECK_BTVER2_M32: #define __SSE2__ 1
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// CHECK_BTVER2_M32: #define __SSE3__ 1
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@ -1232,6 +1235,7 @@
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// CHECK_BTVER2_M64: #define __LZCNT__ 1
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// CHECK_BTVER2_M64: #define __MMX__ 1
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// CHECK_BTVER2_M64: #define __POPCNT__ 1
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// CHECK_BTVER2_M64: #define __PRFCHW__ 1
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// CHECK_BTVER2_M64: #define __SSE2_MATH__ 1
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// CHECK_BTVER2_M64: #define __SSE2__ 1
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// CHECK_BTVER2_M64: #define __SSE3__ 1
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@ -1258,6 +1262,7 @@
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// CHECK_BDVER1_M32: #define __MMX__ 1
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// CHECK_BDVER1_M32: #define __PCLMUL__ 1
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// CHECK_BDVER1_M32: #define __POPCNT__ 1
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// CHECK_BDVER1_M32: #define __PRFCHW__ 1
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// CHECK_BDVER1_M32: #define __SSE2_MATH__ 1
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// CHECK_BDVER1_M32: #define __SSE2__ 1
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// CHECK_BDVER1_M32: #define __SSE3__ 1
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@ -1285,6 +1290,7 @@
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// CHECK_BDVER1_M64: #define __MMX__ 1
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// CHECK_BDVER1_M64: #define __PCLMUL__ 1
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// CHECK_BDVER1_M64: #define __POPCNT__ 1
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// CHECK_BDVER1_M64: #define __PRFCHW__ 1
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// CHECK_BDVER1_M64: #define __SSE2_MATH__ 1
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// CHECK_BDVER1_M64: #define __SSE2__ 1
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// CHECK_BDVER1_M64: #define __SSE3__ 1
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@ -1317,6 +1323,7 @@
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// CHECK_BDVER2_M32: #define __MMX__ 1
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// CHECK_BDVER2_M32: #define __PCLMUL__ 1
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// CHECK_BDVER2_M32: #define __POPCNT__ 1
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// CHECK_BDVER2_M32: #define __PRFCHW__ 1
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// CHECK_BDVER2_M32: #define __SSE2_MATH__ 1
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// CHECK_BDVER2_M32: #define __SSE2__ 1
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// CHECK_BDVER2_M32: #define __SSE3__ 1
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@ -1348,6 +1355,7 @@
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// CHECK_BDVER2_M64: #define __MMX__ 1
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// CHECK_BDVER2_M64: #define __PCLMUL__ 1
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// CHECK_BDVER2_M64: #define __POPCNT__ 1
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// CHECK_BDVER2_M64: #define __PRFCHW__ 1
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// CHECK_BDVER2_M64: #define __SSE2_MATH__ 1
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// CHECK_BDVER2_M64: #define __SSE2__ 1
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// CHECK_BDVER2_M64: #define __SSE3__ 1
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@ -215,3 +215,24 @@
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// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck --check-prefix=MCX16 %s
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// MCX16: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
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// RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -x c -E -dM -o - %s | FileCheck --check-prefix=PRFCHW %s
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// PRFCHW: #define __PRFCHW__ 1
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// RUN: %clang -target i386-unknown-unknown -march=btver2 -mno-prfchw -x c -E -dM -o - %s | FileCheck --check-prefix=NOPRFCHW %s
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// NOPRFCHW-NOT: #define __PRFCHW__ 1
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// RUN: %clang -target i386-unknown-unknown -march=atom -m3dnow -x c -E -dM -o - %s | FileCheck --check-prefix=3DNOWPRFCHW %s
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// 3DNOWPRFCHW: #define __PRFCHW__ 1
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// RUN: %clang -target i386-unknown-unknown -march=atom -mno-prfchw -m3dnow -x c -E -dM -o - %s | FileCheck --check-prefix=3DNOWNOPRFCHW %s
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// 3DNOWNOPRFCHW-NOT: #define __PRFCHW__ 1
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// RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -mno-3dnow -x c -E -dM -o - %s | FileCheck --check-prefix=NO3DNOWPRFCHW %s
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// NO3DNOWPRFCHW: #define __PRFCHW__ 1
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