forked from OSchip/llvm-project
[CostModel]Replace FixedVectorType by VectorType in costgetIntrinsicInstrCost
This patch replaces FixedVectorType by VectorType in getIntrinsicInstrCost in BasicTTIImpl.h. It re-arranges the scalable type test earlier return and add tests for scalable types. Depends on D91532 Differential Revision: https://reviews.llvm.org/D92094
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@ -1202,14 +1202,11 @@ public:
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if (ICA.isTypeBasedOnly())
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return getTypeBasedIntrinsicInstrCost(ICA, CostKind);
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// TODO: Handle scalable vectors?
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Type *RetTy = ICA.getReturnType();
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if (isa<ScalableVectorType>(RetTy))
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return BaseT::getIntrinsicInstrCost(ICA, CostKind);
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ElementCount VF = ICA.getVectorFactor();
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ElementCount RetVF =
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(RetTy->isVectorTy() ? cast<FixedVectorType>(RetTy)->getElementCount()
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(RetTy->isVectorTy() ? cast<VectorType>(RetTy)->getElementCount()
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: ElementCount::getFixed(1));
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assert((RetVF.isScalar() || VF.isScalar()) &&
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"VF > 1 and RetVF is a vector type");
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@ -1238,6 +1235,8 @@ public:
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return thisT()->getMemcpyCost(ICA.getInst());
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case Intrinsic::masked_scatter: {
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if (isa<ScalableVectorType>(RetTy))
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return BaseT::getIntrinsicInstrCost(ICA, CostKind);
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assert(VF.isScalar() && "Can't vectorize types here.");
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const Value *Mask = Args[3];
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bool VarMask = !isa<Constant>(Mask);
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@ -1247,6 +1246,8 @@ public:
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VarMask, Alignment, CostKind, I);
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}
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case Intrinsic::masked_gather: {
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if (isa<ScalableVectorType>(RetTy))
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return BaseT::getIntrinsicInstrCost(ICA, CostKind);
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assert(VF.isScalar() && "Can't vectorize types here.");
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const Value *Mask = Args[2];
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bool VarMask = !isa<Constant>(Mask);
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@ -1265,17 +1266,23 @@ public:
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case Intrinsic::vector_reduce_fmin:
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case Intrinsic::vector_reduce_umax:
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case Intrinsic::vector_reduce_umin: {
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if (isa<ScalableVectorType>(RetTy))
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return BaseT::getIntrinsicInstrCost(ICA, CostKind);
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IntrinsicCostAttributes Attrs(IID, RetTy, Args[0]->getType(), FMF, 1, I);
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return getTypeBasedIntrinsicInstrCost(Attrs, CostKind);
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}
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case Intrinsic::vector_reduce_fadd:
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case Intrinsic::vector_reduce_fmul: {
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if (isa<ScalableVectorType>(RetTy))
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return BaseT::getIntrinsicInstrCost(ICA, CostKind);
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IntrinsicCostAttributes Attrs(
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IID, RetTy, {Args[0]->getType(), Args[1]->getType()}, FMF, 1, I);
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return getTypeBasedIntrinsicInstrCost(Attrs, CostKind);
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}
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case Intrinsic::fshl:
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case Intrinsic::fshr: {
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if (isa<ScalableVectorType>(RetTy))
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return BaseT::getIntrinsicInstrCost(ICA, CostKind);
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const Value *X = Args[0];
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const Value *Y = Args[1];
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const Value *Z = Args[2];
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@ -1316,6 +1323,9 @@ public:
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return Cost;
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}
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}
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// TODO: Handle the remaining intrinsic with scalable vector type
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if (isa<ScalableVectorType>(RetTy))
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return BaseT::getIntrinsicInstrCost(ICA, CostKind);
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// Assume that we need to scalarize this intrinsic.
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SmallVector<Type *, 4> Types;
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@ -0,0 +1,33 @@
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; Checks getIntrinsicInstrCost in BasicTTIImpl.h with SVE for CTLZ and CCTZ
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; RUN: opt -cost-model -analyze -mtriple=aarch64--linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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; Check for CTLZ
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define void @ctlz_nxv4i32(<vscale x 4 x i32> %A) {
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; CHECK-LABEL: 'ctlz_nxv4i32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = tail call <vscale x 4 x i32> @llvm.ctlz.nxv4i32(<vscale x 4 x i32> %A, i1 true)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
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%1 = tail call <vscale x 4 x i32> @llvm.ctlz.nxv4i32(<vscale x 4 x i32> %A, i1 true)
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ret void
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}
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; Check for CCTZ
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define void @cttz_nxv4i32(<vscale x 4 x i32> %A) {
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; CHECK-LABEL: 'cttz_nxv4i32'
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; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = tail call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %A, i1 true)
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; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
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%1 = tail call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %A, i1 true)
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ret void
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}
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declare <vscale x 4 x i32> @llvm.ctlz.nxv4i32(<vscale x 4 x i32>, i1)
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declare <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32>, i1)
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