forked from OSchip/llvm-project
[AArch64] Always add -tune-cpu argument to -cc1 driver
This patch ensures that we always tune for a given CPU on AArch64 targets when the user specifies the "-mtune=xyz" flag. In the AArch64Subtarget if the tune flag is unset we use the CPU value instead. I've updated the release notes here: llvm/docs/ReleaseNotes.rst and added tests here: clang/test/Driver/aarch64-mtune.c Differential Revision: https://reviews.llvm.org/D110258
This commit is contained in:
David Sherwood
parent
ca889733a2
commit
607fb1bb8c
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@ -192,6 +192,13 @@ Arm and AArch64 Support in Clang
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- Support has been added for the following processors (command-line identifiers in parentheses):
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- Arm Cortex-A510 (``cortex-a510``)
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- The -mtune flag is no longer ignored for AArch64. It is now possible to
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tune code generation for a particular CPU with -mtune without setting any
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architectural features. For example, compiling with
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"-mcpu=generic -mtune=cortex-a57" will not enable any Cortex-A57 specific
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architecture features, but will enable certain optimizations specific to
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Cortex-A57 CPUs and enable the use of a more accurate scheduling model.
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Internal API Changes
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--------------------
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@ -1833,6 +1833,21 @@ void Clang::AddAArch64TargetArgs(const ArgList &Args,
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}
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AddAAPCSVolatileBitfieldArgs(Args, CmdArgs);
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if (const Arg *A = Args.getLastArg(clang::driver::options::OPT_mtune_EQ)) {
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StringRef Name = A->getValue();
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std::string TuneCPU;
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if (Name == "native")
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TuneCPU = std::string(llvm::sys::getHostCPUName());
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else
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TuneCPU = std::string(Name);
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if (!TuneCPU.empty()) {
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CmdArgs.push_back("-tune-cpu");
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CmdArgs.push_back(Args.MakeArgString(TuneCPU));
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}
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}
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}
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void Clang::AddMIPSTargetArgs(const ArgList &Args,
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@ -0,0 +1,42 @@
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// Ensure we support the -mtune flag.
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// There shouldn't be a default -mtune.
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// RUN: %clang -target aarch64-unknown-unknown -c -### %s 2>&1 \
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// RUN: | FileCheck %s -check-prefix=NOTUNE
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// NOTUNE-NOT: "-tune-cpu" "generic"
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// RUN: %clang -target aarch64-unknown-unknown -c -### %s -mtune=generic 2>&1 \
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// RUN: | FileCheck %s -check-prefix=GENERIC
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// GENERIC: "-tune-cpu" "generic"
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// RUN: %clang -target aarch64-unknown-unknown -c -### %s -mtune=neoverse-n1 2>&1 \
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// RUN: | FileCheck %s -check-prefix=NEOVERSE-N1
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// NEOVERSE-N1: "-tune-cpu" "neoverse-n1"
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// RUN: %clang -target aarch64-unknown-unknown -c -### %s -mtune=thunderx2t99 2>&1 \
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// RUN: | FileCheck %s -check-prefix=THUNDERX2T99
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// THUNDERX2T99: "-tune-cpu" "thunderx2t99"
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// Check interaction between march and mtune.
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// RUN: %clang -target aarch64-unknown-unknown -c -### %s -march=armv8-a 2>&1 \
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// RUN: | FileCheck %s -check-prefix=MARCHARMV8A
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// MARCHARMV8A: "-target-cpu" "generic"
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// MARCHARMV8A-NOT: "-tune-cpu" "generic"
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// RUN: %clang -target aarch64-unknown-unknown -c -### %s -march=armv8-a -mtune=cortex-a75 2>&1 \
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// RUN: | FileCheck %s -check-prefix=MARCHARMV8A-A75
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// MARCHARMV8A-A75: "-target-cpu" "generic"
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// MARCHARMV8A-A75: "-tune-cpu" "cortex-a75"
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// Check interaction between mcpu and mtune.
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// RUN: %clang -target aarch64-unknown-unknown -c -### %s -mcpu=thunderx 2>&1 \
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// RUN: | FileCheck %s -check-prefix=MCPUTHUNDERX
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// MCPUTHUNDERX: "-target-cpu" "thunderx"
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// MCPUTHUNDERX-NOT: "-tune-cpu"
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// RUN: %clang -target aarch64-unknown-unknown -c -### %s -mcpu=cortex-a75 -mtune=cortex-a57 2>&1 \
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// RUN: | FileCheck %s -check-prefix=MCPUA75-MTUNEA57
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// MCPUA75-MTUNEA57: "-target-cpu" "cortex-a75"
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// MCPUA75-MTUNEA57: "-tune-cpu" "cortex-a57"
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@ -74,6 +74,10 @@ Changes to the AArch64 Backend
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------------------------------
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* Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures.
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* The compiler now recognises the "tune-cpu" function attribute to support
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the use of the -mtune frontend flag. This allows certain scheduling features
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and optimisations to be enabled independently of the architecture. If the
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"tune-cpu" attribute is absent it tunes according to the "target-cpu".
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Changes to the ARM Backend
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--------------------------
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@ -50,15 +50,17 @@ static cl::opt<bool>
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static cl::opt<bool> UseAA("aarch64-use-aa", cl::init(true),
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cl::desc("Enable the use of AA during codegen."));
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AArch64Subtarget &
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AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
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StringRef CPUString) {
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AArch64Subtarget &AArch64Subtarget::initializeSubtargetDependencies(
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StringRef FS, StringRef CPUString, StringRef TuneCPUString) {
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// Determine default and user-specified characteristics
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if (CPUString.empty())
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CPUString = "generic";
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ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FS);
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if (TuneCPUString.empty())
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TuneCPUString = CPUString;
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ParseSubtargetFeatures(CPUString, TuneCPUString, FS);
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initializeProperties();
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return *this;
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@ -198,18 +200,20 @@ void AArch64Subtarget::initializeProperties() {
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}
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AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
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const std::string &TuneCPU,
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const std::string &FS,
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const TargetMachine &TM, bool LittleEndian,
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unsigned MinSVEVectorSizeInBitsOverride,
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unsigned MaxSVEVectorSizeInBitsOverride)
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: AArch64GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
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: AArch64GenSubtargetInfo(TT, CPU, TuneCPU, FS),
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ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
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CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
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IsLittle(LittleEndian),
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MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
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MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),
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FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS, CPU)),
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TSInfo(), TLInfo(TM, *this) {
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FrameLowering(),
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InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU)), TSInfo(),
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TLInfo(TM, *this) {
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if (AArch64::isX18ReservedByDefault(TT))
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ReserveXRegister.set(18);
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@ -298,7 +298,8 @@ private:
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/// passed in feature string so that we can use initializer lists for
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/// subtarget initialization.
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AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
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StringRef CPUString);
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StringRef CPUString,
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StringRef TuneCPUString);
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/// Initialize properties based on the selected processor family.
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void initializeProperties();
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@ -307,8 +308,8 @@ public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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AArch64Subtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS, const TargetMachine &TM,
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bool LittleEndian,
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const std::string &TuneCPU, const std::string &FS,
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const TargetMachine &TM, bool LittleEndian,
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unsigned MinSVEVectorSizeInBitsOverride = 0,
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unsigned MaxSVEVectorSizeInBitsOverride = 0);
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@ -355,10 +355,13 @@ AArch64TargetMachine::~AArch64TargetMachine() = default;
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const AArch64Subtarget *
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AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
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Attribute CPUAttr = F.getFnAttribute("target-cpu");
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Attribute TuneAttr = F.getFnAttribute("tune-cpu");
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Attribute FSAttr = F.getFnAttribute("target-features");
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std::string CPU =
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CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
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std::string TuneCPU =
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TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
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std::string FS =
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FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
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@ -399,6 +402,7 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
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Key += "SVEMax";
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Key += std::to_string(MaxSVEVectorSize);
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Key += CPU;
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Key += TuneCPU;
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Key += FS;
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auto &I = SubtargetMap[Key];
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@ -407,8 +411,8 @@ AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
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isLittle, MinSVEVectorSize,
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I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, TuneCPU, FS,
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*this, isLittle, MinSVEVectorSize,
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MaxSVEVectorSize);
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}
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return I.get();
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@ -29,6 +29,7 @@ std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
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std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) {
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AArch64Subtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM,
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/* isLittle */ false);
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return std::make_unique<AArch64InstrInfo>(ST);
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@ -26,6 +26,7 @@ std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
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std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) {
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AArch64Subtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM,
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/* isLittle */ false);
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return std::make_unique<AArch64InstrInfo>(ST);
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