forked from OSchip/llvm-project
[mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics)
llvm-svn: 190509
This commit is contained in:
Daniel Sanders
parent
c531daefd9
commit
607952bdad
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@ -1225,15 +1225,15 @@ class CTCMSA_DESC {
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bit hasSideEffects = 1;
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}
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class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", int_mips_div_s_b, MSA128B>;
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class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", int_mips_div_s_h, MSA128H>;
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class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", int_mips_div_s_w, MSA128W>;
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class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", int_mips_div_s_d, MSA128D>;
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class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128B>;
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class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128H>;
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class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128W>;
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class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128D>;
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class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", int_mips_div_u_b, MSA128B>;
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class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", int_mips_div_u_h, MSA128H>;
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class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", int_mips_div_u_w, MSA128W>;
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class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", int_mips_div_u_d, MSA128D>;
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class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128B>;
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class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128H>;
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class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128W>;
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class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128D>;
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class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, MSA128H,
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MSA128B, MSA128B>, IsCommutable;
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@ -160,6 +160,8 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
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setOperationAction(ISD::STORE, Ty, Legal);
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setOperationAction(ISD::ADD, Ty, Legal);
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setOperationAction(ISD::SDIV, Ty, Legal);
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setOperationAction(ISD::UDIV, Ty, Legal);
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}
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void MipsSETargetLowering::
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@ -877,6 +879,16 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
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return lowerMSABranchIntr(Op, DAG, MipsISD::VALL_ZERO);
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case Intrinsic::mips_bz_v:
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return lowerMSABranchIntr(Op, DAG, MipsISD::VANY_ZERO);
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case Intrinsic::mips_div_s_b:
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case Intrinsic::mips_div_s_h:
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case Intrinsic::mips_div_s_w:
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case Intrinsic::mips_div_s_d:
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return lowerMSABinaryIntr(Op, DAG, ISD::SDIV);
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case Intrinsic::mips_div_u_b:
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case Intrinsic::mips_div_u_h:
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case Intrinsic::mips_div_u_w:
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case Intrinsic::mips_div_u_d:
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return lowerMSABinaryIntr(Op, DAG, ISD::UDIV);
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}
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}
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@ -91,6 +91,71 @@ declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>) nounwind
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; CHECK: st.d
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; CHECK: .size llvm_mips_div_s_d_test
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;
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define void @div_s_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_div_s_b_ARG1
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%1 = load <16 x i8>* @llvm_mips_div_s_b_ARG2
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%2 = sdiv <16 x i8> %0, %1
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store <16 x i8> %2, <16 x i8>* @llvm_mips_div_s_b_RES
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ret void
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}
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; CHECK: div_s_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
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; CHECK: div_s.b
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; CHECK: st.b
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; CHECK: .size div_s_b_test
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define void @div_s_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_div_s_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_div_s_h_ARG2
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%2 = sdiv <8 x i16> %0, %1
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store <8 x i16> %2, <8 x i16>* @llvm_mips_div_s_h_RES
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ret void
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}
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; CHECK: div_s_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: div_s.h
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; CHECK: st.h
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; CHECK: .size div_s_h_test
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define void @div_s_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_div_s_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_div_s_w_ARG2
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%2 = sdiv <4 x i32> %0, %1
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store <4 x i32> %2, <4 x i32>* @llvm_mips_div_s_w_RES
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ret void
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}
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; CHECK: div_s_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: div_s.w
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; CHECK: st.w
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; CHECK: .size div_s_w_test
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define void @div_s_d_test() nounwind {
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entry:
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%0 = load <2 x i64>* @llvm_mips_div_s_d_ARG1
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%1 = load <2 x i64>* @llvm_mips_div_s_d_ARG2
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%2 = sdiv <2 x i64> %0, %1
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store <2 x i64> %2, <2 x i64>* @llvm_mips_div_s_d_RES
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ret void
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}
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; CHECK: div_s_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: div_s.d
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; CHECK: st.d
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; CHECK: .size div_s_d_test
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;
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@llvm_mips_div_u_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
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@llvm_mips_div_u_b_ARG2 = global <16 x i8> <i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>, align 16
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@llvm_mips_div_u_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
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@ -179,6 +244,71 @@ declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>) nounwind
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; CHECK: st.d
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; CHECK: .size llvm_mips_div_u_d_test
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;
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define void @div_u_b_test() nounwind {
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entry:
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%0 = load <16 x i8>* @llvm_mips_div_u_b_ARG1
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%1 = load <16 x i8>* @llvm_mips_div_u_b_ARG2
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%2 = udiv <16 x i8> %0, %1
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store <16 x i8> %2, <16 x i8>* @llvm_mips_div_u_b_RES
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ret void
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}
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; CHECK: div_u_b_test:
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; CHECK: ld.b
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; CHECK: ld.b
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; CHECK: div_u.b
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; CHECK: st.b
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; CHECK: .size div_u_b_test
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define void @div_u_h_test() nounwind {
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entry:
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%0 = load <8 x i16>* @llvm_mips_div_u_h_ARG1
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%1 = load <8 x i16>* @llvm_mips_div_u_h_ARG2
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%2 = udiv <8 x i16> %0, %1
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store <8 x i16> %2, <8 x i16>* @llvm_mips_div_u_h_RES
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ret void
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}
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; CHECK: div_u_h_test:
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; CHECK: ld.h
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; CHECK: ld.h
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; CHECK: div_u.h
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; CHECK: st.h
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; CHECK: .size div_u_h_test
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define void @div_u_w_test() nounwind {
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entry:
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%0 = load <4 x i32>* @llvm_mips_div_u_w_ARG1
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%1 = load <4 x i32>* @llvm_mips_div_u_w_ARG2
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%2 = udiv <4 x i32> %0, %1
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store <4 x i32> %2, <4 x i32>* @llvm_mips_div_u_w_RES
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ret void
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}
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; CHECK: div_u_w_test:
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; CHECK: ld.w
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; CHECK: ld.w
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; CHECK: div_u.w
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; CHECK: st.w
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; CHECK: .size div_u_w_test
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define void @div_u_d_test() nounwind {
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entry:
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%0 = load <2 x i64>* @llvm_mips_div_u_d_ARG1
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%1 = load <2 x i64>* @llvm_mips_div_u_d_ARG2
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%2 = udiv <2 x i64> %0, %1
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store <2 x i64> %2, <2 x i64>* @llvm_mips_div_u_d_RES
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ret void
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}
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; CHECK: div_u_d_test:
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; CHECK: ld.d
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; CHECK: ld.d
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; CHECK: div_u.d
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; CHECK: st.d
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; CHECK: .size div_u_d_test
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;
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@llvm_mips_dotp_s_h_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3,
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i8 4, i8 5, i8 6, i8 7,
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i8 8, i8 9, i8 10, i8 11,
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