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[RISCV] Add ImmArg to intrinsics 

llvm-svn: 356358
This commit is contained in:
Alex Bradbury 2019-03-18 06:01:27 +00:00
parent d94db9364d
commit 60444ad16f
1 changed files with 6 additions and 6 deletions
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12
llvm/include/llvm/IR/IntrinsicsRISCV.td
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@ -18,13 +18,13 @@ let TargetPrefix = "riscv" in {
class MaskedAtomicRMW32Intrinsic
: Intrinsic<[llvm_i32_ty],
[llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
[IntrArgMemOnly, NoCapture<0>]>;
[IntrArgMemOnly, NoCapture<0>, ImmArg<3>]>;
class MaskedAtomicRMW32WithSextIntrinsic
: Intrinsic<[llvm_i32_ty],
[llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
llvm_i32_ty],
[IntrArgMemOnly, NoCapture<0>]>;
[IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
def int_riscv_masked_atomicrmw_xchg_i32 : MaskedAtomicRMW32Intrinsic;
def int_riscv_masked_atomicrmw_add_i32 : MaskedAtomicRMW32Intrinsic;
@ -38,18 +38,18 @@ def int_riscv_masked_atomicrmw_umin_i32 : MaskedAtomicRMW32Intrinsic;
def int_riscv_masked_cmpxchg_i32
: Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty,
llvm_i32_ty, llvm_i32_ty],
[IntrArgMemOnly, NoCapture<0>]>;
[IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
class MaskedAtomicRMW64Intrinsic
: Intrinsic<[llvm_i64_ty],
[llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty],
[IntrArgMemOnly, NoCapture<0>]>;
[IntrArgMemOnly, NoCapture<0>, ImmArg<3>]>;
class MaskedAtomicRMW64WithSextIntrinsic
: Intrinsic<[llvm_i64_ty],
[llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty,
llvm_i64_ty],
[IntrArgMemOnly, NoCapture<0>]>;
[IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
def int_riscv_masked_atomicrmw_xchg_i64 : MaskedAtomicRMW64Intrinsic;
def int_riscv_masked_atomicrmw_add_i64 : MaskedAtomicRMW64Intrinsic;
@ -63,6 +63,6 @@ def int_riscv_masked_atomicrmw_umin_i64 : MaskedAtomicRMW64Intrinsic;
def int_riscv_masked_cmpxchg_i64
: Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty, llvm_i64_ty, llvm_i64_ty,
llvm_i64_ty, llvm_i64_ty],
[IntrArgMemOnly, NoCapture<0>]>;
[IntrArgMemOnly, NoCapture<0>, ImmArg<4>]>;
} // TargetPrefix = "riscv"