forked from OSchip/llvm-project
Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle
zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. llvm-svn: 174429
This commit is contained in:
Jyotsna Verma
parent
7a0e212f6f
commit
6031625b03
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@ -97,7 +97,14 @@ public:
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SDNode *SelectAdd(SDNode *N);
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bool isConstExtProfitable(SDNode *N) const;
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// Include the pieces autogenerated from the target description.
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// XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
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// [1..128], used in cmpb.gtu instructions.
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inline SDValue XformU7ToU7M1Imm(signed Imm) {
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assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
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return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
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}
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// Include the pieces autogenerated from the target description.
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#include "HexagonGenDAGISel.inc"
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};
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} // end anonymous namespace
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@ -3812,6 +3812,212 @@ def CMPbGTUri_V4 : MInst<(outs PredRegs:$dst),
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u7ExtPred:$src2))]>,
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Requires<[HasV4T]>, ImmRegRel;
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// SDNode for converting immediate C to C-1.
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def DEC_CONST_BYTE : SDNodeXForm<imm, [{
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// Return the byte immediate const-1 as an SDNode.
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int32_t imm = N->getSExtValue();
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return XformU7ToU7M1Imm(imm);
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}]>;
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// For the sequence
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// zext( seteq ( and(Rs, 255), u8))
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// Generate
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// Pd=cmpb.eq(Rs, #u8)
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// if (Pd.new) Rd=#1
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// if (!Pd.new) Rd=#0
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def : Pat <(i32 (zext (i1 (seteq (i32 (and (i32 IntRegs:$Rs), 255)),
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u8ExtPred:$u8)))),
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(i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
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(u8ExtPred:$u8))),
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1, 0))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( setne ( and(Rs, 255), u8))
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// Generate
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// Pd=cmpb.eq(Rs, #u8)
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// if (Pd.new) Rd=#0
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// if (!Pd.new) Rd=#1
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def : Pat <(i32 (zext (i1 (setne (i32 (and (i32 IntRegs:$Rs), 255)),
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u8ExtPred:$u8)))),
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(i32 (TFR_condset_ii (i1 (CMPbEQri_V4 (i32 IntRegs:$Rs),
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(u8ExtPred:$u8))),
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0, 1))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( seteq (Rs, and(Rt, 255)))
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// Generate
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// Pd=cmpb.eq(Rs, Rt)
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// if (Pd.new) Rd=#1
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// if (!Pd.new) Rd=#0
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def : Pat <(i32 (zext (i1 (seteq (i32 IntRegs:$Rt),
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(i32 (and (i32 IntRegs:$Rs), 255)))))),
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(i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
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(i32 IntRegs:$Rt))),
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1, 0))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( setne (Rs, and(Rt, 255)))
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// Generate
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// Pd=cmpb.eq(Rs, Rt)
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// if (Pd.new) Rd=#0
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// if (!Pd.new) Rd=#1
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def : Pat <(i32 (zext (i1 (setne (i32 IntRegs:$Rt),
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(i32 (and (i32 IntRegs:$Rs), 255)))))),
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(i32 (TFR_condset_ii (i1 (CMPbEQrr_ubub_V4 (i32 IntRegs:$Rs),
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(i32 IntRegs:$Rt))),
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0, 1))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( setugt ( and(Rs, 255), u8))
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// Generate
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// Pd=cmpb.gtu(Rs, #u8)
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// if (Pd.new) Rd=#1
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// if (!Pd.new) Rd=#0
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def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 255)),
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u8ExtPred:$u8)))),
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(i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
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(u8ExtPred:$u8))),
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1, 0))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( setugt ( and(Rs, 254), u8))
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// Generate
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// Pd=cmpb.gtu(Rs, #u8)
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// if (Pd.new) Rd=#1
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// if (!Pd.new) Rd=#0
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def : Pat <(i32 (zext (i1 (setugt (i32 (and (i32 IntRegs:$Rs), 254)),
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u8ExtPred:$u8)))),
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(i32 (TFR_condset_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$Rs),
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(u8ExtPred:$u8))),
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1, 0))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( setult ( Rs, Rt))
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// Generate
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// Pd=cmp.ltu(Rs, Rt)
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// if (Pd.new) Rd=#1
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// if (!Pd.new) Rd=#0
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// cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
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def : Pat <(i32 (zext (i1 (setult (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
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(i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt),
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(i32 IntRegs:$Rs))),
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1, 0))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( setlt ( Rs, Rt))
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// Generate
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// Pd=cmp.lt(Rs, Rt)
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// if (Pd.new) Rd=#1
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// if (!Pd.new) Rd=#0
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// cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
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def : Pat <(i32 (zext (i1 (setlt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
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(i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt),
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(i32 IntRegs:$Rs))),
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1, 0))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( setugt ( Rs, Rt))
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// Generate
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// Pd=cmp.gtu(Rs, Rt)
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// if (Pd.new) Rd=#1
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// if (!Pd.new) Rd=#0
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def : Pat <(i32 (zext (i1 (setugt (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
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(i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs),
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(i32 IntRegs:$Rt))),
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1, 0))>,
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Requires<[HasV4T]>;
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// This pattern interefers with coremark performance, not implementing at this
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// time.
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// For the sequence
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// zext( setgt ( Rs, Rt))
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// Generate
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// Pd=cmp.gt(Rs, Rt)
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// if (Pd.new) Rd=#1
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// if (!Pd.new) Rd=#0
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// For the sequence
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// zext( setuge ( Rs, Rt))
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// Generate
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// Pd=cmp.ltu(Rs, Rt)
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// if (Pd.new) Rd=#0
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// if (!Pd.new) Rd=#1
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// cmp.ltu(Rs, Rt) -> cmp.gtu(Rt, Rs)
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def : Pat <(i32 (zext (i1 (setuge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
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(i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rt),
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(i32 IntRegs:$Rs))),
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0, 1))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( setge ( Rs, Rt))
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// Generate
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// Pd=cmp.lt(Rs, Rt)
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// if (Pd.new) Rd=#0
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// if (!Pd.new) Rd=#1
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// cmp.lt(Rs, Rt) -> cmp.gt(Rt, Rs)
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def : Pat <(i32 (zext (i1 (setge (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
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(i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rt),
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(i32 IntRegs:$Rs))),
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0, 1))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( setule ( Rs, Rt))
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// Generate
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// Pd=cmp.gtu(Rs, Rt)
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// if (Pd.new) Rd=#0
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// if (!Pd.new) Rd=#1
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def : Pat <(i32 (zext (i1 (setule (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
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(i32 (TFR_condset_ii (i1 (CMPGTUrr (i32 IntRegs:$Rs),
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(i32 IntRegs:$Rt))),
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0, 1))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( setle ( Rs, Rt))
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// Generate
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// Pd=cmp.gt(Rs, Rt)
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// if (Pd.new) Rd=#0
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// if (!Pd.new) Rd=#1
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def : Pat <(i32 (zext (i1 (setle (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))))),
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(i32 (TFR_condset_ii (i1 (CMPGTrr (i32 IntRegs:$Rs),
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(i32 IntRegs:$Rt))),
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0, 1))>,
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Requires<[HasV4T]>;
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// For the sequence
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// zext( setult ( and(Rs, 255), u8))
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// Use the isdigit transformation below
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// Generate code of the form 'mux_ii(cmpbgtu(Rdd, C-1),0,1)'
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// for C code of the form r = ((c>='0') & (c<='9')) ? 1 : 0;.
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// The isdigit transformation relies on two 'clever' aspects:
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// 1) The data type is unsigned which allows us to eliminate a zero test after
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// biasing the expression by 48. We are depending on the representation of
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// the unsigned types, and semantics.
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// 2) The front end has converted <= 9 into < 10 on entry to LLVM
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//
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// For the C code:
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// retval = ((c>='0') & (c<='9')) ? 1 : 0;
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// The code is transformed upstream of llvm into
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// retval = (c-48) < 10 ? 1 : 0;
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let AddedComplexity = 139 in
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def : Pat <(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
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u7StrictPosImmPred:$src2)))),
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(i32 (MUX_ii (i1 (CMPbGTUri_V4 (i32 IntRegs:$src1),
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(DEC_CONST_BYTE u7StrictPosImmPred:$src2))),
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0, 1))>,
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Requires<[HasV4T]>;
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// Pd=cmpb.gtu(Rs,Rt)
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let isCompare = 1, validSubTargets = HasV4SubT, CextOpcode = "CMPbGTU",
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InputType = "reg" in
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@ -0,0 +1,115 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
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target triple = "hexagon"
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define i32 @Func_3Ugt(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp ugt i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3Uge(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp uge i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3Ult(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp ult i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3Ule(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp ule i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3Ueq(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp eq i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3Une(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp ne i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3UneC(i32 %Enum_Par_Val) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp ne i32 %Enum_Par_Val, 122
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3gt(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK: mux
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%cmp = icmp sgt i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3ge(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp sge i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3lt(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp slt i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3le(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp sle i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3eq(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp eq i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3ne(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp ne i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3neC(i32 %Enum_Par_Val) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp ne i32 %Enum_Par_Val, 122
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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@ -0,0 +1,115 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
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target triple = "hexagon"
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define i32 @Func_3Ugt(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp ugt i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3Uge(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp uge i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3Ult(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp ult i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3Ule(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp ule i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3Ueq(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp eq i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3Une(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%cmp = icmp ne i32 %Enum_Par_Val, %pv2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3UneC(i32 %Enum_Par_Val) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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||||
%cmp = icmp ne i32 %Enum_Par_Val, 122
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3gt(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: mux
|
||||
%cmp = icmp sgt i32 %Enum_Par_Val, %pv2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3ge(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%cmp = icmp sge i32 %Enum_Par_Val, %pv2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3lt(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%cmp = icmp slt i32 %Enum_Par_Val, %pv2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3le(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%cmp = icmp sle i32 %Enum_Par_Val, %pv2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3eq(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%cmp = icmp eq i32 %Enum_Par_Val, %pv2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3ne(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%cmp = icmp ne i32 %Enum_Par_Val, %pv2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3neC(i32 %Enum_Par_Val) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%cmp = icmp ne i32 %Enum_Par_Val, 122
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
|
||||
target triple = "hexagon"
|
||||
|
||||
@Enum_global = external global i8
|
||||
|
||||
define i32 @Func_3(i32) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%conv = and i32 %0, 255
|
||||
%cmp = icmp eq i32 %conv, 2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3b(i32) nounwind readonly {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%1 = load i8* @Enum_global, align 1, !tbaa !0
|
||||
%2 = trunc i32 %0 to i8
|
||||
%cmp = icmp ne i8 %1, %2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3c(i32) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%conv = and i32 %0, 255
|
||||
%cmp = icmp eq i32 %conv, 2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3d(i32) nounwind readonly {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%1 = load i8* @Enum_global, align 1, !tbaa !0
|
||||
%2 = trunc i32 %0 to i8
|
||||
%cmp = icmp eq i8 %1, %2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3e(i32) nounwind readonly {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%1 = load i8* @Enum_global, align 1, !tbaa !0
|
||||
%2 = trunc i32 %0 to i8
|
||||
%cmp = icmp eq i8 %1, %2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3f(i32) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%conv = and i32 %0, 255
|
||||
%cmp = icmp ugt i32 %conv, 2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3g(i32) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: mux
|
||||
%conv = and i32 %0, 255
|
||||
%cmp = icmp ult i32 %conv, 3
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3h(i32) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%conv = and i32 %0, 254
|
||||
%cmp = icmp ult i32 %conv, 2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
define i32 @Func_3i(i32) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-NOT: mux
|
||||
%conv = and i32 %0, 254
|
||||
%cmp = icmp ugt i32 %conv, 1
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
}
|
||||
|
||||
!0 = metadata !{metadata !"omnipotent char", metadata !1}
|
||||
!1 = metadata !{metadata !"Simple C/C++ TBAA"}
|
||||
Loading…
Reference in New Issue