forked from OSchip/llvm-project
[AMDGPU][MC] Enable lds_direct operand for v_readfirstlane_b32, v_readlane_b32 and v_writelane_b32
See bug 40662: https://bugs.llvm.org/show_bug.cgi?id=40662 Reviewers: artem.tamazov, arsenm, rampitec Differential Revision: https://reviews.llvm.org/D58713 llvm-svn: 355312
This commit is contained in:
Dmitry Preobrazhensky
parent
9735d9011a
commit
6023d5990d
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@ -415,6 +415,11 @@ public:
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return isSSrcF16();
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}
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bool isSSrcOrLdsB32() const {
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return isRegOrInlineNoMods(AMDGPU::SRegOrLds_32RegClassID, MVT::i32) ||
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isLiteralImm(MVT::i32) || isExpr();
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}
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bool isVCSrcB32() const {
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return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32);
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}
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@ -2477,6 +2482,73 @@ bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
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return true;
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}
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static bool IsRevOpcode(const unsigned Opcode)
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{
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switch (Opcode) {
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case AMDGPU::V_SUBREV_F32_e32:
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case AMDGPU::V_SUBREV_F32_e64:
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case AMDGPU::V_SUBREV_F32_e32_si:
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case AMDGPU::V_SUBREV_F32_e32_vi:
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case AMDGPU::V_SUBREV_F32_e64_si:
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case AMDGPU::V_SUBREV_F32_e64_vi:
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case AMDGPU::V_SUBREV_I32_e32:
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case AMDGPU::V_SUBREV_I32_e64:
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case AMDGPU::V_SUBREV_I32_e32_si:
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case AMDGPU::V_SUBREV_I32_e64_si:
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case AMDGPU::V_SUBBREV_U32_e32:
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case AMDGPU::V_SUBBREV_U32_e64:
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case AMDGPU::V_SUBBREV_U32_e32_si:
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case AMDGPU::V_SUBBREV_U32_e32_vi:
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case AMDGPU::V_SUBBREV_U32_e64_si:
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case AMDGPU::V_SUBBREV_U32_e64_vi:
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case AMDGPU::V_SUBREV_U32_e32:
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case AMDGPU::V_SUBREV_U32_e64:
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case AMDGPU::V_SUBREV_U32_e32_gfx9:
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case AMDGPU::V_SUBREV_U32_e32_vi:
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case AMDGPU::V_SUBREV_U32_e64_gfx9:
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case AMDGPU::V_SUBREV_U32_e64_vi:
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case AMDGPU::V_SUBREV_F16_e32:
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case AMDGPU::V_SUBREV_F16_e64:
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case AMDGPU::V_SUBREV_F16_e32_vi:
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case AMDGPU::V_SUBREV_F16_e64_vi:
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case AMDGPU::V_SUBREV_U16_e32:
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case AMDGPU::V_SUBREV_U16_e64:
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case AMDGPU::V_SUBREV_U16_e32_vi:
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case AMDGPU::V_SUBREV_U16_e64_vi:
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case AMDGPU::V_SUBREV_CO_U32_e32_gfx9:
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case AMDGPU::V_SUBREV_CO_U32_e64_gfx9:
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case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9:
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case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9:
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case AMDGPU::V_LSHLREV_B32_e32_si:
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case AMDGPU::V_LSHLREV_B32_e64_si:
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case AMDGPU::V_LSHLREV_B16_e32_vi:
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case AMDGPU::V_LSHLREV_B16_e64_vi:
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case AMDGPU::V_LSHLREV_B32_e32_vi:
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case AMDGPU::V_LSHLREV_B32_e64_vi:
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case AMDGPU::V_LSHLREV_B64_vi:
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case AMDGPU::V_LSHRREV_B32_e32_si:
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case AMDGPU::V_LSHRREV_B32_e64_si:
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case AMDGPU::V_LSHRREV_B16_e32_vi:
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case AMDGPU::V_LSHRREV_B16_e64_vi:
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case AMDGPU::V_LSHRREV_B32_e32_vi:
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case AMDGPU::V_LSHRREV_B32_e64_vi:
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case AMDGPU::V_LSHRREV_B64_vi:
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case AMDGPU::V_ASHRREV_I32_e64_si:
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case AMDGPU::V_ASHRREV_I32_e32_si:
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case AMDGPU::V_ASHRREV_I16_e32_vi:
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case AMDGPU::V_ASHRREV_I16_e64_vi:
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case AMDGPU::V_ASHRREV_I32_e32_vi:
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case AMDGPU::V_ASHRREV_I32_e64_vi:
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case AMDGPU::V_ASHRREV_I64_vi:
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case AMDGPU::V_PK_LSHLREV_B16_vi:
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case AMDGPU::V_PK_LSHRREV_B16_vi:
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case AMDGPU::V_PK_ASHRREV_I16_vi:
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return true;
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default:
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return false;
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}
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}
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bool AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
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using namespace SIInstrFlags;
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@ -2511,50 +2583,7 @@ bool AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
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return true;
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// lds_direct is specified as src0. Check additional limitations.
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// FIXME: This is a workaround for bug 37943
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// which allows 64-bit VOP3 opcodes use 32-bit operands.
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if (AMDGPU::getRegOperandSize(getMRI(), Desc, Src0Idx) != 4)
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return false;
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// Documentation does not disable lds_direct for SDWA, but SP3 assembler does.
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// FIXME: This inconsistence needs to be investigated further.
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if (Desc.TSFlags & SIInstrFlags::SDWA)
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return false;
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// The following opcodes do not accept lds_direct which is explicitly stated
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// in AMD documentation. However SP3 disables lds_direct for most other 'rev'
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// opcodes as well (e.g. for v_subrev_u32 but not for v_subrev_f32).
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// FIXME: This inconsistence needs to be investigated further.
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switch (Opcode) {
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case AMDGPU::V_LSHLREV_B32_e32_si:
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case AMDGPU::V_LSHLREV_B32_e64_si:
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case AMDGPU::V_LSHLREV_B16_e32_vi:
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case AMDGPU::V_LSHLREV_B16_e64_vi:
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case AMDGPU::V_LSHLREV_B32_e32_vi:
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case AMDGPU::V_LSHLREV_B32_e64_vi:
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case AMDGPU::V_LSHLREV_B64_vi:
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case AMDGPU::V_LSHRREV_B32_e32_si:
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case AMDGPU::V_LSHRREV_B32_e64_si:
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case AMDGPU::V_LSHRREV_B16_e32_vi:
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case AMDGPU::V_LSHRREV_B16_e64_vi:
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case AMDGPU::V_LSHRREV_B32_e32_vi:
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case AMDGPU::V_LSHRREV_B32_e64_vi:
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case AMDGPU::V_LSHRREV_B64_vi:
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case AMDGPU::V_ASHRREV_I32_e64_si:
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case AMDGPU::V_ASHRREV_I32_e32_si:
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case AMDGPU::V_ASHRREV_I16_e32_vi:
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case AMDGPU::V_ASHRREV_I16_e64_vi:
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case AMDGPU::V_ASHRREV_I32_e32_vi:
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case AMDGPU::V_ASHRREV_I32_e64_vi:
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case AMDGPU::V_ASHRREV_I64_vi:
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case AMDGPU::V_PK_LSHLREV_B16_vi:
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case AMDGPU::V_PK_LSHRREV_B16_vi:
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case AMDGPU::V_PK_ASHRREV_I16_vi:
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return false;
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default:
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return true;
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}
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return (Desc.TSFlags & SIInstrFlags::SDWA) == 0 && !IsRevOpcode(Opcode);
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}
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bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
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@ -97,6 +97,7 @@ static DecodeStatus StaticDecoderName(MCInst &Inst, \
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DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
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DECODE_OPERAND_REG(VGPR_32)
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DECODE_OPERAND_REG(VRegOrLds_32)
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DECODE_OPERAND_REG(VS_32)
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DECODE_OPERAND_REG(VS_64)
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DECODE_OPERAND_REG(VS_128)
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@ -108,6 +109,7 @@ DECODE_OPERAND_REG(VReg_128)
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DECODE_OPERAND_REG(SReg_32)
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DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
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DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
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DECODE_OPERAND_REG(SRegOrLds_32)
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DECODE_OPERAND_REG(SReg_64)
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DECODE_OPERAND_REG(SReg_64_XEXEC)
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DECODE_OPERAND_REG(SReg_128)
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@ -469,6 +471,10 @@ MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
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return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
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return decodeSrcOp(OPW32, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
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return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
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}
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@ -500,6 +506,13 @@ MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
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return decodeOperand_SReg_32(Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
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// table-gen generated disassembler doesn't care about operand types
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// leaving only registry class so SSrc_32 operand turns into SReg_32
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// and therefore we accept immediates and literals here as well
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return decodeSrcOp(OPW32, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
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return decodeSrcOp(OPW64, Val);
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}
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@ -71,6 +71,8 @@ public:
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DecodeStatus convertMIMGInst(MCInst &MI) const;
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MCOperand decodeOperand_VGPR_32(unsigned Val) const;
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MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
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MCOperand decodeOperand_VS_32(unsigned Val) const;
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MCOperand decodeOperand_VS_64(unsigned Val) const;
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MCOperand decodeOperand_VS_128(unsigned Val) const;
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@ -84,6 +86,7 @@ public:
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MCOperand decodeOperand_SReg_32(unsigned Val) const;
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MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
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MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
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MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const;
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MCOperand decodeOperand_SReg_64(unsigned Val) const;
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MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
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MCOperand decodeOperand_SReg_128(unsigned Val) const;
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@ -442,6 +442,11 @@ def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
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let AllocationPriority = 7;
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}
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def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
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(add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI, LDS_DIRECT_CLASS)> {
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let isAllocatable = 0;
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}
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def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, v2f32, f64, v4i16, v4f16], 32, (add SGPR_64Regs)> {
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let CopyCost = 1;
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let AllocationPriority = 8;
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@ -511,6 +516,11 @@ def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
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let AllocationPriority = 12;
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}
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def VRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
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(add VGPR_32, LDS_DIRECT_CLASS)> {
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let isAllocatable = 0;
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}
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// Register class for all vector registers (VGPRs + Interploation Registers)
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def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32, v4f16, v4i16], 32, (add VGPR_64)> {
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let Size = 64;
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@ -631,6 +641,12 @@ multiclass RegInlineOperand <string rc, string MatchName>
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defm SSrc : RegImmOperand<"SReg", "SSrc">;
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def SSrcOrLds_b32 : RegisterOperand<SRegOrLds_32> {
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let OperandNamespace = "AMDGPU";
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let OperandType = "OPERAND_REG_IMM_INT32";
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let ParserMatchClass = RegImmMatcher<"SSrcOrLdsB32">;
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}
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//===----------------------------------------------------------------------===//
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// SCSrc_* Operands with an SGPR or a inline constant
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//===----------------------------------------------------------------------===//
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@ -802,9 +802,11 @@ unsigned getRegBitWidth(unsigned RCID) {
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switch (RCID) {
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case AMDGPU::SGPR_32RegClassID:
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case AMDGPU::VGPR_32RegClassID:
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case AMDGPU::VRegOrLds_32RegClassID:
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case AMDGPU::VS_32RegClassID:
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case AMDGPU::SReg_32RegClassID:
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case AMDGPU::SReg_32_XM0RegClassID:
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case AMDGPU::SRegOrLds_32RegClassID:
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return 32;
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case AMDGPU::SGPR_64RegClassID:
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case AMDGPU::VS_64RegClassID:
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@ -142,7 +142,7 @@ defm V_MOV_B32 : VOP1Inst <"v_mov_b32", VOP_I32_I32>;
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// TODO: Make profile for this, there is VOP3 encoding also
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def V_READFIRSTLANE_B32 :
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InstSI <(outs SReg_32:$vdst),
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(ins VGPR_32:$src0),
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(ins VRegOrLds_32:$src0),
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"v_readfirstlane_b32 $vdst, $src0",
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[(set i32:$vdst, (int_amdgcn_readfirstlane i32:$src0))]>,
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Enc32 {
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@ -360,7 +360,7 @@ def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
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def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
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let Outs32 = (outs SReg_32:$vdst);
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let Outs64 = Outs32;
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let Ins32 = (ins VGPR_32:$src0, SCSrc_b32:$src1);
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let Ins32 = (ins VRegOrLds_32:$src0, SCSrc_b32:$src1);
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let Ins64 = Ins32;
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let Asm32 = " $vdst, $src0, $src1";
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let Asm64 = Asm32;
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@ -765,7 +765,7 @@ defm V_SUBBREV_U32 : VOP2be_Real_e32e64_si <0x2a>;
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defm V_READLANE_B32 : VOP2_Real_si <0x01>;
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let InOperandList = (ins SSrc_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in {
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let InOperandList = (ins SSrcOrLds_b32:$src0, SCSrc_b32:$src1, VSrc_b32:$vdst_in) in {
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defm V_WRITELANE_B32 : VOP2_Real_si <0x02>;
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}
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@ -0,0 +1,10 @@
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// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CI
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v_readfirstlane_b32 s0, lds_direct
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// CI: v_readfirstlane_b32 s0, src_lds_direct ; encoding: [0xfe,0x04,0x00,0x7e]
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v_readlane_b32 s0, lds_direct, s0
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// CI: v_readlane_b32 s0, src_lds_direct, s0 ; encoding: [0xfe,0x00,0x00,0x02]
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v_writelane_b32 v0, lds_direct, s0
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// CI: v_writelane_b32 v0, src_lds_direct, s0 ; encoding: [0xfe,0x00,0x00,0x04]
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@ -5,55 +5,77 @@
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//---------------------------------------------------------------------------//
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s_and_b32 s2, lds_direct, s1
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// NOGFX9: error
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// NOGFX9: error: invalid operand for instruction
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//---------------------------------------------------------------------------//
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// lds_direct may not be used with V_{LSHL,LSHR,ASHL}REV opcodes
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// lds_direct may not be used with "REV" opcodes
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//---------------------------------------------------------------------------//
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v_ashrrev_i16 v0, lds_direct, v0
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// NOGFX9: error
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// NOGFX9: error: invalid use of lds_direct
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v_ashrrev_i32 v0, lds_direct, v0
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// NOGFX9: error
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// NOGFX9: error: invalid use of lds_direct
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v_lshlrev_b16 v0, lds_direct, v0
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// NOGFX9: error
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// NOGFX9: error: invalid use of lds_direct
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v_lshlrev_b32 v0, lds_direct, v0
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// NOGFX9: error
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// NOGFX9: error: invalid use of lds_direct
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v_lshrrev_b16 v0, lds_direct, v0
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// NOGFX9: error
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// NOGFX9: error: invalid use of lds_direct
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v_lshrrev_b32 v0, lds_direct, v0
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// NOGFX9: error
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// NOGFX9: error: invalid use of lds_direct
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v_pk_ashrrev_i16 v0, lds_direct, v0
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// NOGFX9: error
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// NOGFX9: error: invalid use of lds_direct
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v_pk_lshlrev_b16 v0, lds_direct, v0
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// NOGFX9: error
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// NOGFX9: error: invalid use of lds_direct
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v_pk_lshrrev_b16 v0, lds_direct, v0
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// NOGFX9: error
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// NOGFX9: error: invalid use of lds_direct
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v_subbrev_co_u32 v0, vcc, src_lds_direct, v0, vcc
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// NOGFX9: error: invalid use of lds_direct
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v_subrev_co_u32 v0, vcc, src_lds_direct, v0
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// NOGFX9: error: invalid use of lds_direct
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v_subrev_f16 v0, src_lds_direct, v0
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// NOGFX9: error: invalid use of lds_direct
|
||||
|
||||
v_subrev_u16 v0, src_lds_direct, v0
|
||||
// NOGFX9: error: invalid use of lds_direct
|
||||
|
||||
v_subrev_u32 v0, src_lds_direct, v0
|
||||
// NOGFX9: error: invalid use of lds_direct
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// lds_direct may not be used with v_writelane_b32 for VI/GFX9
|
||||
//---------------------------------------------------------------------------//
|
||||
|
||||
v_writelane_b32 v0, lds_direct, s0
|
||||
// NOGFX9: error: instruction not supported on this GPU
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// lds_direct cannot be used with 64-bit and larger operands
|
||||
//---------------------------------------------------------------------------//
|
||||
|
||||
v_add_f64 v[0:1], lds_direct, v[0:1]
|
||||
// NOGFX9: error
|
||||
// NOGFX9: error: invalid operand for instruction
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// Only SRC0 may specify lds_direct
|
||||
//---------------------------------------------------------------------------//
|
||||
|
||||
v_add_i32 v0, v0, lds_direct
|
||||
// NOGFX9: error
|
||||
// NOGFX9: error: invalid use of lds_direct
|
||||
|
||||
v_add_i32 lds_direct, v0, v0
|
||||
// NOGFX9: error
|
||||
// NOGFX9: error: invalid operand for instruction
|
||||
|
||||
v_fma_f32 v0, v0, v0, lds_direct
|
||||
// NOGFX9: error
|
||||
// NOGFX9: error: invalid use of lds_direct
|
||||
|
|
|
|||
|
|
@ -31,6 +31,9 @@ v_fract_f32_e64 v0, src_lds_direct
|
|||
v_cvt_f16_u16 v0, src_lds_direct
|
||||
// GFX9: v_cvt_f16_u16_e32 v0, src_lds_direct ; encoding: [0xfe,0x72,0x00,0x7e]
|
||||
|
||||
v_readfirstlane_b32 s0, src_lds_direct
|
||||
// GFX9: v_readfirstlane_b32 s0, src_lds_direct ; encoding: [0xfe,0x04,0x00,0x7e]
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// VOP2/3
|
||||
//---------------------------------------------------------------------------//
|
||||
|
|
@ -78,6 +81,9 @@ v_min3_i16 v0, src_lds_direct, v0, v0
|
|||
v_max3_f16 v0, src_lds_direct, v0, v0
|
||||
// GFX9: v_max3_f16 v0, src_lds_direct, v0, v0 ; encoding: [0x00,0x00,0xf7,0xd1,0xfe,0x00,0x02,0x04]
|
||||
|
||||
v_readlane_b32 s0, src_lds_direct, s0
|
||||
// GFX9: v_readlane_b32 s0, src_lds_direct, s0 ; encoding: [0x00,0x00,0x89,0xd2,0xfe,0x00,0x00,0x00]
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// VOP3P
|
||||
//---------------------------------------------------------------------------//
|
||||
|
|
@ -107,10 +113,3 @@ v_cmpx_neq_f32 vcc, src_lds_direct, v0
|
|||
|
||||
v_cmp_lt_f16 vcc, lds_direct, v0
|
||||
// GFX9: v_cmp_lt_f16_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0x42,0x7c]
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// FIXME: enable lds_direct for the following opcodes and add tests
|
||||
//---------------------------------------------------------------------------//
|
||||
|
||||
//v_readfirstlane_b32 s0, src_lds_direct
|
||||
//v_readlane_b32 s0, src_lds_direct, s0
|
||||
|
|
|
|||
|
|
@ -17,3 +17,9 @@
|
|||
|
||||
# GFX9: v_cmpx_le_i32_e32 vcc, src_lds_direct, v0 ; encoding: [0xfe,0x00,0xa6,0x7d]
|
||||
0xfe,0x00,0xa6,0x7d
|
||||
|
||||
# GFX9: v_readlane_b32 s0, src_lds_direct, s0 ; encoding: [0x00,0x00,0x89,0xd2,0xfe,0x00,0x00,0x00]
|
||||
0x00,0x00,0x89,0xd2,0xfe,0x00,0x00,0x00
|
||||
|
||||
# GFX9: v_readfirstlane_b32 s0, src_lds_direct ; encoding: [0xfe,0x04,0x00,0x7e]
|
||||
0xfe,0x04,0x00,0x7e
|
||||
|
|
|
|||
Loading…
Reference in New Issue