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[Sparc] This provides support for itineraries on Sparc. 

Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future.

The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this.

As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary.

Phabricator Review: http://reviews.llvm.org/D19359

llvm-svn: 267121
This commit is contained in:
Chris Dewhurst 2016-04-22 08:17:17 +00:00
parent 431fc8af7b
commit 6019702960
5 changed files with 417 additions and 159 deletions
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41
llvm/lib/Target/Sparc/Sparc.td
View File

@ -35,6 +35,9 @@ def FeatureVIS2
def FeatureVIS3 def FeatureVIS3
: SubtargetFeature<"vis3", "IsVIS3", "true", : SubtargetFeature<"vis3", "IsVIS3", "true",
"Enable Visual Instruction Set extensions III">; "Enable Visual Instruction Set extensions III">;
def FeatureLeon
: SubtargetFeature<"leon", "IsLeon", "true",
"Enable LEON extensions">;
def FeatureHardQuad def FeatureHardQuad
: SubtargetFeature<"hard-quad-float", "HasHardQuad", "true", : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
@ -49,6 +52,7 @@ def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
include "SparcRegisterInfo.td" include "SparcRegisterInfo.td"
include "SparcCallingConv.td" include "SparcCallingConv.td"
include "SparcSchedule.td"
include "SparcInstrInfo.td" include "SparcInstrInfo.td"
def SparcInstrInfo : InstrInfo; def SparcInstrInfo : InstrInfo;
@ -90,6 +94,43 @@ def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3]>; FeatureVIS, FeatureVIS2, FeatureVIS3]>;
// LEON 2 FT generic
def : Processor<"leon2", LEON2Itineraries,
[FeatureLeon]>;
// LEON 2 FT (AT697E)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"at697e", LEON2Itineraries,
[FeatureLeon]>;
// LEON 2 FT (AT697F)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"at697f", LEON2Itineraries,
[FeatureLeon]>;
// LEON 3 FT generic
def : Processor<"leon3", LEON3Itineraries,
[FeatureLeon]>;
// LEON 3 FT (UT699)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"ut699", LEON3Itineraries,
[FeatureLeon]>;
// LEON3 FT (GR712RC)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"gr712rc", LEON3Itineraries,
[FeatureLeon]>;
// LEON 4 FT generic
def : Processor<"leon4", LEON4Itineraries,
[FeatureLeon]>;
// LEON 4 FT (GR740)
// TO DO: Place-holder: Processor specific features will be added *very* soon here.
def : Processor<"gr740", LEON4Itineraries,
[FeatureLeon]> {}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Declare the target which we are implementing // Declare the target which we are implementing

122
llvm/lib/Target/Sparc/SparcInstrFormats.td
View File

@ -7,8 +7,9 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,
: Instruction { InstrItinClass itin = NoItinerary>
: Instruction {
field bits<32> Inst; field bits<32> Inst;
let Namespace = "SP"; let Namespace = "SP";
@ -24,6 +25,8 @@ class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
let DecoderNamespace = "Sparc"; let DecoderNamespace = "Sparc";
field bits<32> SoftFail = 0; field bits<32> SoftFail = 0;
let Itinerary = itin;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -31,8 +34,9 @@ class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Format 2 instructions // Format 2 instructions
class F2<dag outs, dag ins, string asmstr, list<dag> pattern> class F2<dag outs, dag ins, string asmstr, list<dag> pattern,
: InstSP<outs, ins, asmstr, pattern> { InstrItinClass itin = NoItinerary>
: InstSP<outs, ins, asmstr, pattern, itin> {
bits<3> op2; bits<3> op2;
bits<22> imm22; bits<22> imm22;
let op = 0; // op = 0 let op = 0; // op = 0
@ -42,8 +46,9 @@ class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
// Specific F2 classes: SparcV8 manual, page 44 // Specific F2 classes: SparcV8 manual, page 44
// //
class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern> class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
: F2<outs, ins, asmstr, pattern> { InstrItinClass itin = NoItinerary>
: F2<outs, ins, asmstr, pattern, itin> {
bits<5> rd; bits<5> rd;
let op2 = op2Val; let op2 = op2Val;
@ -52,7 +57,8 @@ class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
} }
class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr, class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
list<dag> pattern> : F2<outs, ins, asmstr, pattern> { list<dag> pattern, InstrItinClass itin = NoItinerary>
: F2<outs, ins, asmstr, pattern, itin> {
bits<4> cond; bits<4> cond;
let op2 = op2Val; let op2 = op2Val;
@ -61,8 +67,9 @@ class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
} }
class F2_3<bits<3> op2Val, bit annul, bit pred, class F2_3<bits<3> op2Val, bit annul, bit pred,
dag outs, dag ins, string asmstr, list<dag> pattern> dag outs, dag ins, string asmstr, list<dag> pattern,
: InstSP<outs, ins, asmstr, pattern> { InstrItinClass itin = NoItinerary>
: InstSP<outs, ins, asmstr, pattern, itin> {
bits<2> cc; bits<2> cc;
bits<4> cond; bits<4> cond;
bits<19> imm19; bits<19> imm19;
@ -77,9 +84,9 @@ class F2_3<bits<3> op2Val, bit annul, bit pred,
let Inst{18-0} = imm19; let Inst{18-0} = imm19;
} }
class F2_4<bits<3> cond, bit annul, bit pred, class F2_4<bits<3> cond, bit annul, bit pred, dag outs, dag ins,
dag outs, dag ins, string asmstr, list<dag> pattern> string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
: InstSP<outs, ins, asmstr, pattern> { : InstSP<outs, ins, asmstr, pattern, itin> {
bits<16> imm16; bits<16> imm16;
bits<5> rs1; bits<5> rs1;
@ -100,8 +107,9 @@ class F2_4<bits<3> cond, bit annul, bit pred,
// Format #3 instruction classes in the Sparc // Format #3 instruction classes in the Sparc
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class F3<dag outs, dag ins, string asmstr, list<dag> pattern> class F3<dag outs, dag ins, string asmstr, list<dag> pattern,
: InstSP<outs, ins, asmstr, pattern> { InstrItinClass itin = NoItinerary>
: InstSP<outs, ins, asmstr, pattern, itin> {
bits<5> rd; bits<5> rd;
bits<6> op3; bits<6> op3;
bits<5> rs1; bits<5> rs1;
@ -114,7 +122,8 @@ class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
// Specific F3 classes: SparcV8 manual, page 44 // Specific F3 classes: SparcV8 manual, page 44
// //
class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins, class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
: F3<outs, ins, asmstr, pattern, itin> {
bits<8> asi; bits<8> asi;
bits<5> rs2; bits<5> rs2;
@ -127,13 +136,14 @@ class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
} }
class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
list<dag> pattern> : F3_1_asi<opVal, op3val, outs, ins, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
asmstr, pattern> { : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> {
let asi = 0; let asi = 0;
} }
class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
: F3<outs, ins, asmstr, pattern, itin> {
bits<13> simm13; bits<13> simm13;
let op = opVal; let op = opVal;
@ -145,7 +155,8 @@ class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
// floating-point // floating-point
class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
: F3<outs, ins, asmstr, pattern, itin> {
bits<5> rs2; bits<5> rs2;
let op = opVal; let op = opVal;
@ -157,7 +168,8 @@ class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
// floating-point unary operations. // floating-point unary operations.
class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
: F3<outs, ins, asmstr, pattern, itin> {
bits<5> rs2; bits<5> rs2;
let op = opVal; let op = opVal;
@ -170,7 +182,8 @@ class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
// floating-point compares. // floating-point compares.
class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary>
: F3<outs, ins, asmstr, pattern, itin> {
bits<5> rs2; bits<5> rs2;
let op = opVal; let op = opVal;
@ -182,7 +195,8 @@ class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
// Shift by register rs2. // Shift by register rs2.
class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
: F3<outs, ins, asmstr, pattern, itin> {
bit x = xVal; // 1 for 64-bit shifts. bit x = xVal; // 1 for 64-bit shifts.
bits<5> rs2; bits<5> rs2;
@ -196,7 +210,8 @@ class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
// Shift by immediate. // Shift by immediate.
class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr>
: F3<outs, ins, asmstr, pattern, itin> {
bit x = xVal; // 1 for 64-bit shifts. bit x = xVal; // 1 for 64-bit shifts.
bits<6> shcnt; // shcnt32 / shcnt64. bits<6> shcnt; // shcnt32 / shcnt64.
@ -210,17 +225,21 @@ class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
// Define rr and ri shift instructions with patterns. // Define rr and ri shift instructions with patterns.
multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
ValueType VT, RegisterClass RC> { ValueType VT, RegisterClass RC,
InstrItinClass itin = IIC_iu_instr> {
def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
!strconcat(OpcStr, " $rs1, $rs2, $rd"), !strconcat(OpcStr, " $rs1, $rs2, $rd"),
[(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>; [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))],
itin>;
def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
!strconcat(OpcStr, " $rs1, $shcnt, $rd"), !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
[(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>; [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))],
itin>;
} }
class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern> class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern,
: InstSP<outs, ins, asmstr, pattern> { InstrItinClass itin = NoItinerary>
: InstSP<outs, ins, asmstr, pattern, itin> {
bits<5> rd; bits<5> rd;
let op = 2; let op = 2;
@ -230,9 +249,9 @@ class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
class F4_1<bits<6> op3, dag outs, dag ins, class F4_1<bits<6> op3, dag outs, dag ins,
string asmstr, list<dag> pattern> string asmstr, list<dag> pattern,
: F4<op3, outs, ins, asmstr, pattern> { InstrItinClass itin = NoItinerary>
: F4<op3, outs, ins, asmstr, pattern, itin> {
bit intcc; bit intcc;
bits<2> cc; bits<2> cc;
bits<4> cond; bits<4> cond;
@ -243,12 +262,12 @@ class F4_1<bits<6> op3, dag outs, dag ins,
let Inst{13} = 0; let Inst{13} = 0;
let Inst{17-14} = cond; let Inst{17-14} = cond;
let Inst{18} = intcc; let Inst{18} = intcc;
} }
class F4_2<bits<6> op3, dag outs, dag ins, class F4_2<bits<6> op3, dag outs, dag ins,
string asmstr, list<dag> pattern> string asmstr, list<dag> pattern,
: F4<op3, outs, ins, asmstr, pattern> { InstrItinClass itin = NoItinerary>
: F4<op3, outs, ins, asmstr, pattern, itin> {
bit intcc; bit intcc;
bits<2> cc; bits<2> cc;
bits<4> cond; bits<4> cond;
@ -262,8 +281,9 @@ class F4_2<bits<6> op3, dag outs, dag ins,
} }
class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins, class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
string asmstr, list<dag> pattern> string asmstr, list<dag> pattern,
: F4<op3, outs, ins, asmstr, pattern> { InstrItinClass itin = NoItinerary>
: F4<op3, outs, ins, asmstr, pattern, itin> {
bits<4> cond; bits<4> cond;
bit intcc; bit intcc;
bits<2> opf_cc; bits<2> opf_cc;
@ -278,8 +298,9 @@ class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
} }
class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins, class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins,
string asmstr, list<dag> pattern> string asmstr, list<dag> pattern,
: F4<op3, outs, ins, asmstr, pattern> { InstrItinClass itin = NoItinerary>
: F4<op3, outs, ins, asmstr, pattern, itin> {
bits <5> rs1; bits <5> rs1;
bits <5> rs2; bits <5> rs2;
let Inst{18-14} = rs1; let Inst{18-14} = rs1;
@ -291,8 +312,9 @@ class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins,
class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins, class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins,
string asmstr, list<dag> pattern> string asmstr, list<dag> pattern,
: F4<op3, outs, ins, asmstr, pattern> { InstrItinClass itin = NoItinerary>
: F4<op3, outs, ins, asmstr, pattern, itin> {
bits<5> rs1; bits<5> rs1;
bits<10> simm10; bits<10> simm10;
let Inst{18-14} = rs1; let Inst{18-14} = rs1;
@ -302,9 +324,10 @@ class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins,
} }
class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, string asmstr, class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins,
list<dag> pattern>: F3<outs, ins, asmstr, pattern> { string asmstr, list<dag> pattern,
InstrItinClass itin = NoItinerary>
: F3<outs, ins, asmstr, pattern, itin> {
bits<4> cond; bits<4> cond;
bits<2> cc; bits<2> cc;
@ -317,15 +340,20 @@ class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, string asmstr,
} }
class TRAPSPrr<bits<6> op3Val, dag outs, dag ins, string asmstr, class TRAPSPrr<bits<6> op3Val, dag outs, dag ins,
list<dag> pattern>: TRAPSP<op3Val, 0, outs, ins, asmstr, pattern> { string asmstr, list<dag> pattern,
InstrItinClass itin = NoItinerary>
: TRAPSP<op3Val, 0, outs, ins, asmstr, pattern, itin> {
bits<5> rs2; bits<5> rs2;
let Inst{10-5} = 0; let Inst{10-5} = 0;
let Inst{4-0} = rs2; let Inst{4-0} = rs2;
} }
class TRAPSPri<bits<6> op3Val, dag outs, dag ins, string asmstr,
list<dag> pattern>: TRAPSP<op3Val, 1, outs, ins, asmstr, pattern> { class TRAPSPri<bits<6> op3Val, dag outs, dag ins,
string asmstr, list<dag> pattern,
InstrItinClass itin = NoItinerary>
: TRAPSP<op3Val, 1, outs, ins, asmstr, pattern, itin> {
bits<8> imm; bits<8> imm;
let Inst{10-8} = 0; let Inst{10-8} = 0;

290
llvm/lib/Target/Sparc/SparcInstrInfo.td
View File

@ -264,53 +264,61 @@ def CPCC_012 : CPCC_VAL<47>; // 0 or 1 or 2
/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode, multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
RegisterClass RC, ValueType Ty, Operand immOp> { RegisterClass RC, ValueType Ty, Operand immOp,
InstrItinClass itin = IIC_iu_instr> {
def rr : F3_1<2, Op3Val, def rr : F3_1<2, Op3Val,
(outs RC:$rd), (ins RC:$rs1, RC:$rs2), (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
!strconcat(OpcStr, " $rs1, $rs2, $rd"), !strconcat(OpcStr, " $rs1, $rs2, $rd"),
[(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>; [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
itin>;
def ri : F3_2<2, Op3Val, def ri : F3_2<2, Op3Val,
(outs RC:$rd), (ins RC:$rs1, immOp:$simm13), (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
!strconcat(OpcStr, " $rs1, $simm13, $rd"), !strconcat(OpcStr, " $rs1, $simm13, $rd"),
[(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>; [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
itin>;
} }
/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
/// pattern. /// pattern.
multiclass F3_12np<string OpcStr, bits<6> Op3Val> { multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {
def rr : F3_1<2, Op3Val, def rr : F3_1<2, Op3Val,
(outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
!strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
itin>;
def ri : F3_2<2, Op3Val, def ri : F3_2<2, Op3Val,
(outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
!strconcat(OpcStr, " $rs1, $simm13, $rd"), []>; !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
itin>;
} }
// Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
RegisterClass RC, ValueType Ty> { RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_iu_instr> {
def rr : F3_1<3, Op3Val, def rr : F3_1<3, Op3Val,
(outs RC:$dst), (ins MEMrr:$addr), (outs RC:$dst), (ins MEMrr:$addr),
!strconcat(OpcStr, " [$addr], $dst"), !strconcat(OpcStr, " [$addr], $dst"),
[(set Ty:$dst, (OpNode ADDRrr:$addr))]>; [(set Ty:$dst, (OpNode ADDRrr:$addr))],
itin>;
def ri : F3_2<3, Op3Val, def ri : F3_2<3, Op3Val,
(outs RC:$dst), (ins MEMri:$addr), (outs RC:$dst), (ins MEMri:$addr),
!strconcat(OpcStr, " [$addr], $dst"), !strconcat(OpcStr, " [$addr], $dst"),
[(set Ty:$dst, (OpNode ADDRri:$addr))]>; [(set Ty:$dst, (OpNode ADDRri:$addr))],
itin>;
} }
// TODO: Instructions of the LoadASI class are currently asm only; hooking up // TODO: Instructions of the LoadASI class are currently asm only; hooking up
// CodeGen's address spaces to use these is a future task. // CodeGen's address spaces to use these is a future task.
class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
RegisterClass RC, ValueType Ty> : RegisterClass RC, ValueType Ty, InstrItinClass itin = NoItinerary> :
F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi), F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
!strconcat(OpcStr, "a [$addr] $asi, $dst"), !strconcat(OpcStr, "a [$addr] $asi, $dst"),
[]>; []>;
// LoadA multiclass - As above, but also define alternate address space variant // LoadA multiclass - As above, but also define alternate address space variant
multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val, multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
Load<OpcStr, Op3Val, OpNode, RC, Ty> { InstrItinClass itin = NoItinerary> :
Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {
def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>; def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>;
} }
@ -318,38 +326,43 @@ multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
// It is unlikely that general-purpose code could make use of it. // It is unlikely that general-purpose code could make use of it.
// CAS is preferred for sparc v9. // CAS is preferred for sparc v9.
def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr), def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
"ldstub [$addr], $dst", []>; "ldstub [$addr], $dst", []>;
def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr), def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
"ldstub [$addr], $dst", []>; "ldstub [$addr], $dst", []>;
def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst), def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst),
(ins MEMrr:$addr, i8imm:$asi), (ins MEMrr:$addr, i8imm:$asi),
"ldstuba [$addr] $asi, $dst", []>; "ldstuba [$addr] $asi, $dst", []>;
// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
RegisterClass RC, ValueType Ty> { RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
def rr : F3_1<3, Op3Val, def rr : F3_1<3, Op3Val,
(outs), (ins MEMrr:$addr, RC:$rd), (outs), (ins MEMrr:$addr, RC:$rd),
!strconcat(OpcStr, " $rd, [$addr]"), !strconcat(OpcStr, " $rd, [$addr]"),
[(OpNode Ty:$rd, ADDRrr:$addr)]>; [(OpNode Ty:$rd, ADDRrr:$addr)],
itin>;
def ri : F3_2<3, Op3Val, def ri : F3_2<3, Op3Val,
(outs), (ins MEMri:$addr, RC:$rd), (outs), (ins MEMri:$addr, RC:$rd),
!strconcat(OpcStr, " $rd, [$addr]"), !strconcat(OpcStr, " $rd, [$addr]"),
[(OpNode Ty:$rd, ADDRri:$addr)]>; [(OpNode Ty:$rd, ADDRri:$addr)],
itin>;
} }
// TODO: Instructions of the StoreASI class are currently asm only; hooking up // TODO: Instructions of the StoreASI class are currently asm only; hooking up
// CodeGen's address spaces to use these is a future task. // CodeGen's address spaces to use these is a future task.
class StoreASI<string OpcStr, bits<6> Op3Val, class StoreASI<string OpcStr, bits<6> Op3Val,
SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
InstrItinClass itin = IIC_st> :
F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi), F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
!strconcat(OpcStr, "a $rd, [$addr] $asi"), !strconcat(OpcStr, "a $rd, [$addr] $asi"),
[]>; [],
itin>;
multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val, multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
InstrItinClass itin = IIC_st> :
Store<OpcStr, Op3Val, OpNode, RC, Ty> { Store<OpcStr, Op3Val, OpNode, RC, Ty> {
def Arr : StoreASI<OpcStr, StoreAOp3Val, OpNode, RC, Ty>; def Arr : StoreASI<OpcStr, StoreAOp3Val, OpNode, RC, Ty, itin>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -444,16 +457,16 @@ let DecoderMethod = "DecodeLoadInt" in {
} }
let DecoderMethod = "DecodeLoadIntPair" in let DecoderMethod = "DecodeLoadIntPair" in
defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32>; defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>;
// Section B.2 - Load Floating-point Instructions, p. 92 // Section B.2 - Load Floating-point Instructions, p. 92
let DecoderMethod = "DecodeLoadFP" in { let DecoderMethod = "DecodeLoadFP" in {
defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>; defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>;
def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32>, def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32, IIC_iu_or_fpu_instr>,
Requires<[HasV9]>; Requires<[HasV9]>;
} }
let DecoderMethod = "DecodeLoadDFP" in { let DecoderMethod = "DecodeLoadDFP" in {
defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>; defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64, IIC_ldd>;
def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>, def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>,
Requires<[HasV9]>; Requires<[HasV9]>;
} }
@ -464,7 +477,7 @@ let DecoderMethod = "DecodeLoadQFP" in
let DecoderMethod = "DecodeLoadCP" in let DecoderMethod = "DecodeLoadCP" in
defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>; defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>;
let DecoderMethod = "DecodeLoadCPPair" in let DecoderMethod = "DecodeLoadCPPair" in
defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32>; defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>;
let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in { let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in {
let rd = 0 in { let rd = 0 in {
@ -479,9 +492,9 @@ let DecoderMethod = "DecodeLoadFP" in
let Defs = [FSR] in { let Defs = [FSR] in {
let rd = 0 in { let rd = 0 in {
def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
"ld [$addr], %fsr", []>; "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr), def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
"ld [$addr], %fsr", []>; "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
} }
let rd = 1 in { let rd = 1 in {
def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
@ -499,7 +512,7 @@ let DecoderMethod = "DecodeStoreInt" in {
} }
let DecoderMethod = "DecodeStoreIntPair" in let DecoderMethod = "DecodeStoreIntPair" in
defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32>; defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32, IIC_std>;
// Section B.5 - Store Floating-point Instructions, p. 97 // Section B.5 - Store Floating-point Instructions, p. 97
let DecoderMethod = "DecodeStoreFP" in { let DecoderMethod = "DecodeStoreFP" in {
@ -508,7 +521,7 @@ let DecoderMethod = "DecodeStoreFP" in {
Requires<[HasV9]>; Requires<[HasV9]>;
} }
let DecoderMethod = "DecodeStoreDFP" in { let DecoderMethod = "DecodeStoreDFP" in {
defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>; defm STDF : Store<"std", 0b100111, store, DFPRegs, f64, IIC_std>;
def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>, def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>,
Requires<[HasV9]>; Requires<[HasV9]>;
} }
@ -520,20 +533,20 @@ let DecoderMethod = "DecodeStoreCP" in
defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>; defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>;
let DecoderMethod = "DecodeStoreCPPair" in let DecoderMethod = "DecodeStoreCPPair" in
defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32>; defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>;
let DecoderMethod = "DecodeStoreCP", rd = 0 in { let DecoderMethod = "DecodeStoreCP", rd = 0 in {
let Defs = [CPSR] in { let Defs = [CPSR] in {
def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins), def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins),
"st %csr, [$addr]", []>; "st %csr, [$addr]", [], IIC_st>;
def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins), def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins),
"st %csr, [$addr]", []>; "st %csr, [$addr]", [], IIC_st>;
} }
let Defs = [CPQ] in { let Defs = [CPQ] in {
def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins), def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins),
"std %cq, [$addr]", []>; "std %cq, [$addr]", [], IIC_std>;
def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins), def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins),
"std %cq, [$addr]", []>; "std %cq, [$addr]", [], IIC_std>;
} }
} }
@ -541,15 +554,15 @@ let DecoderMethod = "DecodeStoreFP" in {
let rd = 0 in { let rd = 0 in {
let Defs = [FSR] in { let Defs = [FSR] in {
def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins), def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
"st %fsr, [$addr]", []>; "st %fsr, [$addr]", [], IIC_st>;
def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins), def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
"st %fsr, [$addr]", []>; "st %fsr, [$addr]", [], IIC_st>;
} }
let Defs = [FQ] in { let Defs = [FQ] in {
def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins), def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins),
"std %fq, [$addr]", []>; "std %fq, [$addr]", [], IIC_std>;
def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins), def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins),
"std %fq, [$addr]", []>; "std %fq, [$addr]", [], IIC_std>;
} }
} }
let rd = 1, Defs = [FSR] in { let rd = 1, Defs = [FSR] in {
@ -582,7 +595,8 @@ let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
def SETHIi: F2_1<0b100, def SETHIi: F2_1<0b100,
(outs IntRegs:$rd), (ins i32imm:$imm22), (outs IntRegs:$rd), (ins i32imm:$imm22),
"sethi $imm22, $rd", "sethi $imm22, $rd",
[(set i32:$rd, SETHIimm:$imm22)]>; [(set i32:$rd, SETHIimm:$imm22)],
IIC_iu_instr>;
// Section B.10 - NOP Instruction, p. 105 // Section B.10 - NOP Instruction, p. 105
// (It's a special case of SETHI) // (It's a special case of SETHI)
@ -677,13 +691,13 @@ let Defs = [ICC], rd = 0 in {
// Section B.18 - Multiply Instructions, p. 113 // Section B.18 - Multiply Instructions, p. 113
let Defs = [Y] in { let Defs = [Y] in {
defm UMUL : F3_12np<"umul", 0b001010>; defm UMUL : F3_12np<"umul", 0b001010, IIC_iu_umul>;
defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op>; defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op, IIC_iu_smul>;
} }
let Defs = [Y, ICC] in { let Defs = [Y, ICC] in {
defm UMULCC : F3_12np<"umulcc", 0b011010>; defm UMULCC : F3_12np<"umulcc", 0b011010, IIC_iu_umul>;
defm SMULCC : F3_12np<"smulcc", 0b011011>; defm SMULCC : F3_12np<"smulcc", 0b011011, IIC_iu_smul>;
} }
let Defs = [Y, ICC], Uses = [Y, ICC] in { let Defs = [Y, ICC], Uses = [Y, ICC] in {
@ -692,13 +706,13 @@ let Defs = [Y, ICC], Uses = [Y, ICC] in {
// Section B.19 - Divide Instructions, p. 115 // Section B.19 - Divide Instructions, p. 115
let Uses = [Y], Defs = [Y] in { let Uses = [Y], Defs = [Y] in {
defm UDIV : F3_12np<"udiv", 0b001110>; defm UDIV : F3_12np<"udiv", 0b001110, IIC_iu_div>;
defm SDIV : F3_12np<"sdiv", 0b001111>; defm SDIV : F3_12np<"sdiv", 0b001111, IIC_iu_div>;
} }
let Uses = [Y], Defs = [Y, ICC] in { let Uses = [Y], Defs = [Y, ICC] in {
defm UDIVCC : F3_12np<"udivcc", 0b011110>; defm UDIVCC : F3_12np<"udivcc", 0b011110, IIC_iu_div>;
defm SDIVCC : F3_12np<"sdivcc", 0b011111>; defm SDIVCC : F3_12np<"sdivcc", 0b011111, IIC_iu_div>;
} }
// Section B.20 - SAVE and RESTORE, p. 117 // Section B.20 - SAVE and RESTORE, p. 117
@ -724,26 +738,30 @@ let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
// conditional branch class: // conditional branch class:
class BranchSP<dag ins, string asmstr, list<dag> pattern> class BranchSP<dag ins, string asmstr, list<dag> pattern>
: F2_2<0b010, 0, (outs), ins, asmstr, pattern>; : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>;
// conditional branch with annul class: // conditional branch with annul class:
class BranchSPA<dag ins, string asmstr, list<dag> pattern> class BranchSPA<dag ins, string asmstr, list<dag> pattern>
: F2_2<0b010, 1, (outs), ins, asmstr, pattern>; : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>;
// Conditional branch class on %icc|%xcc with predication: // Conditional branch class on %icc|%xcc with predication:
multiclass IPredBranch<string regstr, list<dag> CCPattern> { multiclass IPredBranch<string regstr, list<dag> CCPattern> {
def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond), def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
!strconcat("b$cond ", !strconcat(regstr, ", $imm19")), !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
CCPattern>; CCPattern,
IIC_iu_instr>;
def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond), def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
!strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")), !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
[]>; [],
IIC_iu_instr>;
def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond), def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
!strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")), !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
[]>; [],
IIC_iu_instr>;
def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond), def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
!strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")), !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
[]>; [],
IIC_iu_instr>;
} }
} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
@ -779,26 +797,26 @@ let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
// floating-point conditional branch class: // floating-point conditional branch class:
class FPBranchSP<dag ins, string asmstr, list<dag> pattern> class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
: F2_2<0b110, 0, (outs), ins, asmstr, pattern>; : F2_2<0b110, 0, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;
// floating-point conditional branch with annul class: // floating-point conditional branch with annul class:
class FPBranchSPA<dag ins, string asmstr, list<dag> pattern> class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
: F2_2<0b110, 1, (outs), ins, asmstr, pattern>; : F2_2<0b110, 1, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;
// Conditional branch class on %fcc0-%fcc3 with predication: // Conditional branch class on %fcc0-%fcc3 with predication:
multiclass FPredBranch { multiclass FPredBranch {
def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond, def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
FCCRegs:$cc), FCCRegs:$cc),
"fb$cond $cc, $imm19", []>; "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>;
def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond, def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
FCCRegs:$cc), FCCRegs:$cc),
"fb$cond,a $cc, $imm19", []>; "fb$cond,a $cc, $imm19", [], IIC_fpu_normal_instr>;
def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond, def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
FCCRegs:$cc), FCCRegs:$cc),
"fb$cond,pn $cc, $imm19", []>; "fb$cond,pn $cc, $imm19", [], IIC_fpu_normal_instr>;
def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond, def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
FCCRegs:$cc), FCCRegs:$cc),
"fb$cond,a,pn $cc, $imm19", []>; "fb$cond,a,pn $cc, $imm19", [], IIC_fpu_normal_instr>;
} }
} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
@ -837,7 +855,9 @@ def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
let Uses = [O6], let Uses = [O6],
hasDelaySlot = 1, isCall = 1 in { hasDelaySlot = 1, isCall = 1 in {
def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops), def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
"call $disp", []> { "call $disp",
[],
IIC_jmp_or_call> {
bits<30> disp; bits<30> disp;
let op = 1; let op = 1;
let Inst{29-0} = disp; let Inst{29-0} = disp;
@ -848,11 +868,13 @@ let Uses = [O6],
def CALLrr : F3_1<2, 0b111000, def CALLrr : F3_1<2, 0b111000,
(outs), (ins MEMrr:$ptr, variable_ops), (outs), (ins MEMrr:$ptr, variable_ops),
"call $ptr", "call $ptr",
[(call ADDRrr:$ptr)]>; [(call ADDRrr:$ptr)],
IIC_jmp_or_call>;
def CALLri : F3_2<2, 0b111000, def CALLri : F3_2<2, 0b111000,
(outs), (ins MEMri:$ptr, variable_ops), (outs), (ins MEMri:$ptr, variable_ops),
"call $ptr", "call $ptr",
[(call ADDRri:$ptr)]>; [(call ADDRri:$ptr)],
IIC_jmp_or_call>;
} }
} }
@ -861,10 +883,16 @@ let Uses = [O6],
// JMPL Instruction. // JMPL Instruction.
let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
DecoderMethod = "DecodeJMPL" in { DecoderMethod = "DecodeJMPL" in {
def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr), def JMPLrr: F3_1<2, 0b111000,
"jmpl $addr, $dst", []>; (outs IntRegs:$dst), (ins MEMrr:$addr),
def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr), "jmpl $addr, $dst",
"jmpl $addr, $dst", []>; [],
IIC_jmp_or_call>;
def JMPLri: F3_2<2, 0b111000,
(outs IntRegs:$dst), (ins MEMri:$addr),
"jmpl $addr, $dst",
[],
IIC_jmp_or_call>;
} }
// Section A.3 - Synthetic Instructions, p. 85 // Section A.3 - Synthetic Instructions, p. 85
@ -872,21 +900,33 @@ let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
isCodeGenOnly = 1 in { isCodeGenOnly = 1 in {
let rd = 0, rs1 = 15 in let rd = 0, rs1 = 15 in
def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), def RETL: F3_2<2, 0b111000,
"jmp %o7+$val", [(retflag simm13:$val)]>; (outs), (ins i32imm:$val),
"jmp %o7+$val",
[(retflag simm13:$val)],
IIC_jmp_or_call>;
let rd = 0, rs1 = 31 in let rd = 0, rs1 = 31 in
def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), def RET: F3_2<2, 0b111000,
"jmp %i7+$val", []>; (outs), (ins i32imm:$val),
"jmp %i7+$val",
[],
IIC_jmp_or_call>;
} }
// Section B.26 - Return from Trap Instruction // Section B.26 - Return from Trap Instruction
let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in { isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr), def RETTrr : F3_1<2, 0b111001,
"rett $addr", []>; (outs), (ins MEMrr:$addr),
def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr), "rett $addr",
"rett $addr", []>; [],
IIC_jmp_or_call>;
def RETTri : F3_2<2, 0b111001,
(outs), (ins MEMri:$addr),
"rett $addr",
[],
IIC_jmp_or_call>;
} }
@ -894,21 +934,25 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
// conditional branch class: // conditional branch class:
let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
{ {
def TRAPrr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2, def TRAPrr : TRAPSPrr<0b111010,
CCOp:$cond), (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
"t$cond $rs1 + $rs2", []>; "t$cond $rs1 + $rs2",
def TRAPri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm, []>;
CCOp:$cond), def TRAPri : TRAPSPri<0b111010,
"t$cond $rs1 + $imm", []>; (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
"t$cond $rs1 + $imm",
[]>;
} }
multiclass TRAP<string regStr> { multiclass TRAP<string regStr> {
def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2, def rr : TRAPSPrr<0b111010,
CCOp:$cond), (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
!strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>; !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"),
def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm, []>;
CCOp:$cond), def ri : TRAPSPri<0b111010,
!strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>; (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
!strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"),
[]>;
} }
let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
@ -1010,11 +1054,13 @@ let rd = 0 in {
def FITOS : F3_3u<2, 0b110100, 0b011000100, def FITOS : F3_3u<2, 0b110100, 0b011000100,
(outs FPRegs:$rd), (ins FPRegs:$rs2), (outs FPRegs:$rd), (ins FPRegs:$rs2),
"fitos $rs2, $rd", "fitos $rs2, $rd",
[(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>; [(set FPRegs:$rd, (SPitof FPRegs:$rs2))],
IIC_fpu_fast_instr>;
def FITOD : F3_3u<2, 0b110100, 0b011001000, def FITOD : F3_3u<2, 0b110100, 0b011001000,
(outs DFPRegs:$rd), (ins FPRegs:$rs2), (outs DFPRegs:$rd), (ins FPRegs:$rs2),
"fitod $rs2, $rd", "fitod $rs2, $rd",
[(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>; [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))],
IIC_fpu_fast_instr>;
def FITOQ : F3_3u<2, 0b110100, 0b011001100, def FITOQ : F3_3u<2, 0b110100, 0b011001100,
(outs QFPRegs:$rd), (ins FPRegs:$rs2), (outs QFPRegs:$rd), (ins FPRegs:$rs2),
"fitoq $rs2, $rd", "fitoq $rs2, $rd",
@ -1025,11 +1071,13 @@ def FITOQ : F3_3u<2, 0b110100, 0b011001100,
def FSTOI : F3_3u<2, 0b110100, 0b011010001, def FSTOI : F3_3u<2, 0b110100, 0b011010001,
(outs FPRegs:$rd), (ins FPRegs:$rs2), (outs FPRegs:$rd), (ins FPRegs:$rs2),
"fstoi $rs2, $rd", "fstoi $rs2, $rd",
[(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>; [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))],
IIC_fpu_fast_instr>;
def FDTOI : F3_3u<2, 0b110100, 0b011010010, def FDTOI : F3_3u<2, 0b110100, 0b011010010,
(outs FPRegs:$rd), (ins DFPRegs:$rs2), (outs FPRegs:$rd), (ins DFPRegs:$rs2),
"fdtoi $rs2, $rd", "fdtoi $rs2, $rd",
[(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>; [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))],
IIC_fpu_fast_instr>;
def FQTOI : F3_3u<2, 0b110100, 0b011010011, def FQTOI : F3_3u<2, 0b110100, 0b011010011,
(outs FPRegs:$rd), (ins QFPRegs:$rs2), (outs FPRegs:$rd), (ins QFPRegs:$rs2),
"fqtoi $rs2, $rd", "fqtoi $rs2, $rd",
@ -1040,7 +1088,8 @@ def FQTOI : F3_3u<2, 0b110100, 0b011010011,
def FSTOD : F3_3u<2, 0b110100, 0b011001001, def FSTOD : F3_3u<2, 0b110100, 0b011001001,
(outs DFPRegs:$rd), (ins FPRegs:$rs2), (outs DFPRegs:$rd), (ins FPRegs:$rs2),
"fstod $rs2, $rd", "fstod $rs2, $rd",
[(set f64:$rd, (fextend f32:$rs2))]>; [(set f64:$rd, (fextend f32:$rs2))],
IIC_fpu_stod>;
def FSTOQ : F3_3u<2, 0b110100, 0b011001101, def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
(outs QFPRegs:$rd), (ins FPRegs:$rs2), (outs QFPRegs:$rd), (ins FPRegs:$rs2),
"fstoq $rs2, $rd", "fstoq $rs2, $rd",
@ -1049,7 +1098,8 @@ def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
def FDTOS : F3_3u<2, 0b110100, 0b011000110, def FDTOS : F3_3u<2, 0b110100, 0b011000110,
(outs FPRegs:$rd), (ins DFPRegs:$rs2), (outs FPRegs:$rd), (ins DFPRegs:$rs2),
"fdtos $rs2, $rd", "fdtos $rs2, $rd",
[(set f32:$rd, (fround f64:$rs2))]>; [(set f32:$rd, (fround f64:$rs2))],
IIC_fpu_fast_instr>;
def FDTOQ : F3_3u<2, 0b110100, 0b011001110, def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
(outs QFPRegs:$rd), (ins DFPRegs:$rs2), (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
"fdtoq $rs2, $rd", "fdtoq $rs2, $rd",
@ -1073,22 +1123,26 @@ def FMOVS : F3_3u<2, 0b110100, 0b000000001,
def FNEGS : F3_3u<2, 0b110100, 0b000000101, def FNEGS : F3_3u<2, 0b110100, 0b000000101,
(outs FPRegs:$rd), (ins FPRegs:$rs2), (outs FPRegs:$rd), (ins FPRegs:$rs2),
"fnegs $rs2, $rd", "fnegs $rs2, $rd",
[(set f32:$rd, (fneg f32:$rs2))]>; [(set f32:$rd, (fneg f32:$rs2))],
IIC_fpu_negs>;
def FABSS : F3_3u<2, 0b110100, 0b000001001, def FABSS : F3_3u<2, 0b110100, 0b000001001,
(outs FPRegs:$rd), (ins FPRegs:$rs2), (outs FPRegs:$rd), (ins FPRegs:$rs2),
"fabss $rs2, $rd", "fabss $rs2, $rd",
[(set f32:$rd, (fabs f32:$rs2))]>; [(set f32:$rd, (fabs f32:$rs2))],
IIC_fpu_abs>;
// Floating-point Square Root Instructions, p.145 // Floating-point Square Root Instructions, p.145
def FSQRTS : F3_3u<2, 0b110100, 0b000101001, def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
(outs FPRegs:$rd), (ins FPRegs:$rs2), (outs FPRegs:$rd), (ins FPRegs:$rs2),
"fsqrts $rs2, $rd", "fsqrts $rs2, $rd",
[(set f32:$rd, (fsqrt f32:$rs2))]>; [(set f32:$rd, (fsqrt f32:$rs2))],
IIC_fpu_sqrts>;
def FSQRTD : F3_3u<2, 0b110100, 0b000101010, def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs2), (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
"fsqrtd $rs2, $rd", "fsqrtd $rs2, $rd",
[(set f64:$rd, (fsqrt f64:$rs2))]>; [(set f64:$rd, (fsqrt f64:$rs2))],
IIC_fpu_sqrtd>;
def FSQRTQ : F3_3u<2, 0b110100, 0b000101011, def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
(outs QFPRegs:$rd), (ins QFPRegs:$rs2), (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
"fsqrtq $rs2, $rd", "fsqrtq $rs2, $rd",
@ -1101,11 +1155,13 @@ def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
def FADDS : F3_3<2, 0b110100, 0b001000001, def FADDS : F3_3<2, 0b110100, 0b001000001,
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fadds $rs1, $rs2, $rd", "fadds $rs1, $rs2, $rd",
[(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>; [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))],
IIC_fpu_fast_instr>;
def FADDD : F3_3<2, 0b110100, 0b001000010, def FADDD : F3_3<2, 0b110100, 0b001000010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"faddd $rs1, $rs2, $rd", "faddd $rs1, $rs2, $rd",
[(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>; [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))],
IIC_fpu_fast_instr>;
def FADDQ : F3_3<2, 0b110100, 0b001000011, def FADDQ : F3_3<2, 0b110100, 0b001000011,
(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
"faddq $rs1, $rs2, $rd", "faddq $rs1, $rs2, $rd",
@ -1115,11 +1171,13 @@ def FADDQ : F3_3<2, 0b110100, 0b001000011,
def FSUBS : F3_3<2, 0b110100, 0b001000101, def FSUBS : F3_3<2, 0b110100, 0b001000101,
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fsubs $rs1, $rs2, $rd", "fsubs $rs1, $rs2, $rd",
[(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>; [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))],
IIC_fpu_fast_instr>;
def FSUBD : F3_3<2, 0b110100, 0b001000110, def FSUBD : F3_3<2, 0b110100, 0b001000110,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fsubd $rs1, $rs2, $rd", "fsubd $rs1, $rs2, $rd",
[(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>; [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))],
IIC_fpu_fast_instr>;
def FSUBQ : F3_3<2, 0b110100, 0b001000111, def FSUBQ : F3_3<2, 0b110100, 0b001000111,
(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
"fsubq $rs1, $rs2, $rd", "fsubq $rs1, $rs2, $rd",
@ -1131,11 +1189,13 @@ def FSUBQ : F3_3<2, 0b110100, 0b001000111,
def FMULS : F3_3<2, 0b110100, 0b001001001, def FMULS : F3_3<2, 0b110100, 0b001001001,
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fmuls $rs1, $rs2, $rd", "fmuls $rs1, $rs2, $rd",
[(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>; [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))],
IIC_fpu_muls>;
def FMULD : F3_3<2, 0b110100, 0b001001010, def FMULD : F3_3<2, 0b110100, 0b001001010,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fmuld $rs1, $rs2, $rd", "fmuld $rs1, $rs2, $rd",
[(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>; [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))],
IIC_fpu_muld>;
def FMULQ : F3_3<2, 0b110100, 0b001001011, def FMULQ : F3_3<2, 0b110100, 0b001001011,
(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
"fmulq $rs1, $rs2, $rd", "fmulq $rs1, $rs2, $rd",
@ -1146,7 +1206,8 @@ def FSMULD : F3_3<2, 0b110100, 0b001101001,
(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fsmuld $rs1, $rs2, $rd", "fsmuld $rs1, $rs2, $rd",
[(set f64:$rd, (fmul (fextend f32:$rs1), [(set f64:$rd, (fmul (fextend f32:$rs1),
(fextend f32:$rs2)))]>; (fextend f32:$rs2)))],
IIC_fpu_muld>;
def FDMULQ : F3_3<2, 0b110100, 0b001101110, def FDMULQ : F3_3<2, 0b110100, 0b001101110,
(outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fdmulq $rs1, $rs2, $rd", "fdmulq $rs1, $rs2, $rd",
@ -1157,11 +1218,13 @@ def FDMULQ : F3_3<2, 0b110100, 0b001101110,
def FDIVS : F3_3<2, 0b110100, 0b001001101, def FDIVS : F3_3<2, 0b110100, 0b001001101,
(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
"fdivs $rs1, $rs2, $rd", "fdivs $rs1, $rs2, $rd",
[(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>; [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))],
IIC_fpu_divs>;
def FDIVD : F3_3<2, 0b110100, 0b001001110, def FDIVD : F3_3<2, 0b110100, 0b001001110,
(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fdivd $rs1, $rs2, $rd", "fdivd $rs1, $rs2, $rd",
[(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>; [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))],
IIC_fpu_divd>;
def FDIVQ : F3_3<2, 0b110100, 0b001001111, def FDIVQ : F3_3<2, 0b110100, 0b001001111,
(outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
"fdivq $rs1, $rs2, $rd", "fdivq $rs1, $rs2, $rd",
@ -1179,11 +1242,13 @@ let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
def FCMPS : F3_3c<2, 0b110101, 0b001010001, def FCMPS : F3_3c<2, 0b110101, 0b001010001,
(outs), (ins FPRegs:$rs1, FPRegs:$rs2), (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
"fcmps $rs1, $rs2", "fcmps $rs1, $rs2",
[(SPcmpfcc f32:$rs1, f32:$rs2)]>; [(SPcmpfcc f32:$rs1, f32:$rs2)],
IIC_fpu_fast_instr>;
def FCMPD : F3_3c<2, 0b110101, 0b001010010, def FCMPD : F3_3c<2, 0b110101, 0b001010010,
(outs), (ins DFPRegs:$rs1, DFPRegs:$rs2), (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
"fcmpd $rs1, $rs2", "fcmpd $rs1, $rs2",
[(SPcmpfcc f64:$rs1, f64:$rs2)]>; [(SPcmpfcc f64:$rs1, f64:$rs2)],
IIC_fpu_fast_instr>;
def FCMPQ : F3_3c<2, 0b110101, 0b001010011, def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
(outs), (ins QFPRegs:$rs1, QFPRegs:$rs2), (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
"fcmpq $rs1, $rs2", "fcmpq $rs1, $rs2",
@ -1213,7 +1278,8 @@ let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
def TLS_CALL : InstSP<(outs), def TLS_CALL : InstSP<(outs),
(ins calltarget:$disp, TLSSym:$sym, variable_ops), (ins calltarget:$disp, TLSSym:$sym, variable_ops),
"call $disp, $sym", "call $disp, $sym",
[(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> { [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)],
IIC_jmp_or_call> {
bits<30> disp; bits<30> disp;
let op = 1; let op = 1;
let Inst{29-0} = disp; let Inst{29-0} = disp;

121
llvm/lib/Target/Sparc/SparcSchedule.td Executable file
View File

@ -0,0 +1,121 @@
//===-- SparcSchedule.td - Describe the Sparc Itineries ----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//
def IIC_iu_or_fpu_instr : InstrItinClass;
def IIC_iu_instr : InstrItinClass;
def IIC_fpu_normal_instr : InstrItinClass;
def IIC_fpu_fast_instr : InstrItinClass;
def IIC_jmp_or_call : InstrItinClass;
def IIC_ldd : InstrItinClass;
def IIC_st : InstrItinClass;
def IIC_std : InstrItinClass;
def IIC_iu_smul : InstrItinClass;
def IIC_iu_umul : InstrItinClass;
def IIC_iu_div : InstrItinClass;
def IIC_ticc : InstrItinClass;
def IIC_ldstub : InstrItinClass;
def IIC_fpu_muls : InstrItinClass;
def IIC_fpu_muld : InstrItinClass;
def IIC_fpu_divs : InstrItinClass;
def IIC_fpu_divd : InstrItinClass;
def IIC_fpu_sqrts : InstrItinClass;
def IIC_fpu_sqrtd : InstrItinClass;
def IIC_fpu_abs : InstrItinClass;
def IIC_fpu_movs : InstrItinClass;
def IIC_fpu_negs : InstrItinClass;
def IIC_fpu_stod : InstrItinClass;
def LEONIU : FuncUnit; // integer unit
def LEONFPU : FuncUnit; // floating-point unit
// Ref: http://www.atmel.com/Images/doc4226.pdf
def LEON2Itineraries : ProcessorItineraries<
[LEONIU, LEONFPU], [], [
InstrItinData<IIC_iu_or_fpu_instr, [InstrStage<1, [LEONIU, LEONFPU]>], [1, 1]>,
InstrItinData<IIC_iu_instr, [InstrStage<1, [LEONIU]>], [1, 1]>,
InstrItinData<IIC_fpu_normal_instr, [InstrStage<1, [LEONFPU]>], [7, 1]>,
InstrItinData<IIC_fpu_fast_instr, [InstrStage<1, [LEONFPU]>], [7, 1]>,
InstrItinData<IIC_jmp_or_call, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
InstrItinData<IIC_ldd, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
InstrItinData<IIC_st, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
InstrItinData<IIC_std, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [5, 1]>,
InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [5, 1]>,
InstrItinData<IIC_iu_div, [InstrStage<1, [LEONIU]>], [35, 1]>,
InstrItinData<IIC_ticc, [InstrStage<1, [LEONIU, LEONFPU]>], [4, 1]>,
InstrItinData<IIC_ldstub, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
InstrItinData<IIC_fpu_muls, [InstrStage<1, [LEONFPU]>], [16, 1]>,
InstrItinData<IIC_fpu_muld, [InstrStage<1, [LEONFPU]>], [21, 1]>,
InstrItinData<IIC_fpu_divs, [InstrStage<1, [LEONFPU]>], [20, 1]>,
InstrItinData<IIC_fpu_divd, [InstrStage<1, [LEONFPU]>], [36, 1]>,
InstrItinData<IIC_fpu_sqrts, [InstrStage<1, [LEONFPU]>], [37, 1]>,
InstrItinData<IIC_fpu_sqrtd, [InstrStage<1, [LEONFPU]>], [65, 1]>,
InstrItinData<IIC_fpu_abs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
InstrItinData<IIC_fpu_movs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
InstrItinData<IIC_fpu_negs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
InstrItinData<IIC_fpu_stod, [InstrStage<1, [LEONFPU]>], [2, 1]>
]>;
def LEON3Itineraries : ProcessorItineraries<
[LEONIU, LEONFPU], [], [
InstrItinData<IIC_iu_or_fpu_instr, [InstrStage<1, [LEONIU, LEONFPU]>], [1, 1]>,
InstrItinData<IIC_iu_instr, [InstrStage<1, [LEONIU]>], [1, 1]>,
InstrItinData<IIC_fpu_normal_instr, [InstrStage<1, [LEONFPU]>], [7, 1]>,
InstrItinData<IIC_fpu_fast_instr, [InstrStage<1, [LEONFPU]>], [4, 1]>,
InstrItinData<IIC_jmp_or_call, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
InstrItinData<IIC_ldd, [InstrStage<1, [LEONIU, LEONFPU]>], [2, 1]>,
InstrItinData<IIC_st, [InstrStage<1, [LEONIU, LEONFPU]>], [4, 1]>,
InstrItinData<IIC_std, [InstrStage<1, [LEONIU, LEONFPU]>], [5, 1]>,
InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [1, 1]>,
InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [4, 1]>,
InstrItinData<IIC_iu_div, [InstrStage<1, [LEONIU]>], [35, 1]>,
InstrItinData<IIC_ticc, [InstrStage<1, [LEONIU, LEONFPU]>], [5, 1]>,
InstrItinData<IIC_ldstub, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
InstrItinData<IIC_fpu_muls, [InstrStage<1, [LEONFPU]>], [4, 1]>,
InstrItinData<IIC_fpu_muld, [InstrStage<1, [LEONFPU]>], [4, 1]>,
InstrItinData<IIC_fpu_divs, [InstrStage<1, [LEONFPU]>], [16, 1]>,
InstrItinData<IIC_fpu_divd, [InstrStage<1, [LEONFPU]>], [17, 1]>,
InstrItinData<IIC_fpu_sqrts, [InstrStage<1, [LEONFPU]>], [24, 1]>,
InstrItinData<IIC_fpu_sqrtd, [InstrStage<1, [LEONFPU]>], [25, 1]>,
InstrItinData<IIC_fpu_abs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
InstrItinData<IIC_fpu_movs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
InstrItinData<IIC_fpu_negs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
InstrItinData<IIC_fpu_stod, [InstrStage<1, [LEONFPU]>], [4, 1]>
]>;
def LEON4Itineraries : ProcessorItineraries<
[LEONIU, LEONFPU], [], [
InstrItinData<IIC_iu_or_fpu_instr, [InstrStage<1, [LEONIU, LEONFPU]>], [1, 1]>,
InstrItinData<IIC_iu_instr, [InstrStage<1, [LEONIU]>], [1, 1]>,
InstrItinData<IIC_fpu_normal_instr, [InstrStage<1, [LEONFPU]>], [7, 1]>,
InstrItinData<IIC_fpu_fast_instr, [InstrStage<1, [LEONFPU]>], [4, 1]>,
InstrItinData<IIC_jmp_or_call, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
InstrItinData<IIC_ldd, [InstrStage<1, [LEONIU, LEONFPU]>], [1, 1]>,
InstrItinData<IIC_st, [InstrStage<1, [LEONIU, LEONFPU]>], [1, 1]>,
InstrItinData<IIC_std, [InstrStage<1, [LEONIU, LEONFPU]>], [1, 1]>,
InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [1, 1]>,
InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [4, 1]>,
InstrItinData<IIC_iu_div, [InstrStage<1, [LEONIU]>], [35, 1]>,
InstrItinData<IIC_ticc, [InstrStage<1, [LEONIU, LEONFPU]>], [5, 1]>,
InstrItinData<IIC_ldstub, [InstrStage<1, [LEONIU, LEONFPU]>], [3, 1]>,
InstrItinData<IIC_fpu_muls, [InstrStage<1, [LEONFPU]>], [4, 1]>,
InstrItinData<IIC_fpu_muld, [InstrStage<1, [LEONFPU]>], [4, 1]>,
InstrItinData<IIC_fpu_divs, [InstrStage<1, [LEONFPU]>], [16, 1]>,
InstrItinData<IIC_fpu_divd, [InstrStage<1, [LEONFPU]>], [17, 1]>,
InstrItinData<IIC_fpu_sqrts, [InstrStage<1, [LEONFPU]>], [24, 1]>,
InstrItinData<IIC_fpu_sqrtd, [InstrStage<1, [LEONFPU]>], [25, 1]>,
InstrItinData<IIC_fpu_abs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
InstrItinData<IIC_fpu_movs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
InstrItinData<IIC_fpu_negs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
InstrItinData<IIC_fpu_stod, [InstrStage<1, [LEONFPU]>], [4, 1]>
]>;

2
llvm/lib/Target/Sparc/SparcSubtarget.h
View File

@ -32,6 +32,7 @@ class StringRef;
class SparcSubtarget : public SparcGenSubtargetInfo { class SparcSubtarget : public SparcGenSubtargetInfo {
virtual void anchor(); virtual void anchor();
bool IsV9; bool IsV9;
bool IsLeon;
bool V8DeprecatedInsts; bool V8DeprecatedInsts;
bool IsVIS, IsVIS2, IsVIS3; bool IsVIS, IsVIS2, IsVIS3;
bool Is64Bit; bool Is64Bit;
@ -63,6 +64,7 @@ public:
bool enableMachineScheduler() const override; bool enableMachineScheduler() const override;
bool isV9() const { return IsV9; } bool isV9() const { return IsV9; }
bool isLeon() const { return IsLeon; }
bool isVIS() const { return IsVIS; } bool isVIS() const { return IsVIS; }
bool isVIS2() const { return IsVIS2; } bool isVIS2() const { return IsVIS2; }
bool isVIS3() const { return IsVIS3; } bool isVIS3() const { return IsVIS3; }