forked from OSchip/llvm-project
[RISCV] Replace a custom SDTypeProfile with SDTIntBinOp which should be sufficient here.
On the surface this would be slightly less optimal for the isel table, but due to a tablegen issue with HW mode this ends up generating a smaller isel table.
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@ -716,13 +716,10 @@ let Predicates = [HasStdExtZbs] in
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def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
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(SBEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
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def SDT_RISCVGREVGORC : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>,
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SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>]>;
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def riscv_grevi : SDNode<"RISCVISD::GREVI", SDT_RISCVGREVGORC, []>;
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def riscv_greviw : SDNode<"RISCVISD::GREVIW", SDT_RISCVGREVGORC, []>;
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def riscv_gorci : SDNode<"RISCVISD::GORCI", SDT_RISCVGREVGORC, []>;
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def riscv_gorciw : SDNode<"RISCVISD::GORCIW", SDT_RISCVGREVGORC, []>;
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def riscv_grevi : SDNode<"RISCVISD::GREVI", SDTIntBinOp, []>;
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def riscv_greviw : SDNode<"RISCVISD::GREVIW", SDTIntBinOp, []>;
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def riscv_gorci : SDNode<"RISCVISD::GORCI", SDTIntBinOp, []>;
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def riscv_gorciw : SDNode<"RISCVISD::GORCIW", SDTIntBinOp, []>;
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let Predicates = [HasStdExtZbp] in {
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def : Pat<(riscv_grevi GPR:$rs1, timm:$shamt), (GREVI GPR:$rs1, timm:$shamt)>;
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