forked from OSchip/llvm-project
bpf: remove unnecessary truncate operation
For networking-type bpf program, it often needs to access
packet data. A context data structure is provided to the bpf
programs with two fields:
u32 data;
u32 data_end;
User can access these two fields with ctx->data and ctx->data_end.
During program verification process, the kernel verifier modifies
the bpf program with loading of actual pointer value from kernel
data structure.
r = ctx->data ===> r = actual data start ptr
r = ctx->data_end ===> r = actual data end ptr
A typical program accessing ctx->data like
char *data_ptr = (char *)(long)ctx->data
will result in a 32-bit load followed by a zero extension.
Such an operation is combined into a single LDW in DAG combiner
as bpf LDW does zero extension automatically.
In cases like the below (which can be a result of global value numbering
and partial redundancy elimination before insn selection):
B1:
u32 a = load-32-bit &ctx->data
u64 pa = zext a
...
B2:
u32 b = load-32-bit &ctx->data
u64 pb = zext b
...
B3:
u32 m = PHI(a, b)
u64 pm = zext m
In B3, "pm = zext m" cannot be removed, which although is legal
from compiler perspective, will generate incorrect code after
kernel verification.
This patch recognizes this pattern and traces through PHI node
to see whether the operand of "zext m" is defined with LDWs or not.
If it is, the "zext m" itself can be removed.
The patch also recognizes the pattern where the load and use of
the load value not in the same basic block, where truncate operation
may be removed as well.
The patch handles 1-byte, 2-byte and 4-byte truncation.
Two test cases are added to verify the transformation happens properly
for the above code pattern.
Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 306685
This commit is contained in:
Yonghong Song
parent
1925594ea0
commit
5fbe01b12d
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@ -16,6 +16,7 @@
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#include "BPFRegisterInfo.h"
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#include "BPFSubtarget.h"
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#include "BPFTargetMachine.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -57,6 +58,11 @@ private:
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bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectFIAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
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// Node preprocessing cases
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void PreprocessLoad(SDNode *Node, SelectionDAG::allnodes_iterator I);
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void PreprocessCopyToReg(SDNode *Node);
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void PreprocessTrunc(SDNode *Node, SelectionDAG::allnodes_iterator I);
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// Find constants from a constant structure
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typedef std::vector<unsigned char> val_vec_type;
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bool fillGenericConstant(const DataLayout &DL, const Constant *CV,
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@ -69,9 +75,12 @@ private:
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val_vec_type &Vals, int Offset);
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bool getConstantFieldValue(const GlobalAddressSDNode *Node, uint64_t Offset,
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uint64_t Size, unsigned char *ByteSeq);
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bool checkLoadDef(unsigned DefReg, unsigned match_load_op);
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// Mapping from ConstantStruct global value to corresponding byte-list values
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std::map<const void *, val_vec_type> cs_vals_;
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// Mapping from vreg to load memory opcode
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std::map<unsigned, unsigned> load_to_vreg_;
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};
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} // namespace
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@ -203,89 +212,110 @@ void BPFDAGToDAGISel::Select(SDNode *Node) {
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SelectCode(Node);
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}
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void BPFDAGToDAGISel::PreprocessLoad(SDNode *Node,
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SelectionDAG::allnodes_iterator I) {
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union {
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uint8_t c[8];
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uint16_t s;
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uint32_t i;
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uint64_t d;
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} new_val; // hold up the constant values replacing loads.
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bool to_replace = false;
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SDLoc DL(Node);
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const LoadSDNode *LD = cast<LoadSDNode>(Node);
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uint64_t size = LD->getMemOperand()->getSize();
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if (!size || size > 8 || (size & (size - 1)))
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return;
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SDNode *LDAddrNode = LD->getOperand(1).getNode();
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// Match LDAddr against either global_addr or (global_addr + offset)
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unsigned opcode = LDAddrNode->getOpcode();
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if (opcode == ISD::ADD) {
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SDValue OP1 = LDAddrNode->getOperand(0);
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SDValue OP2 = LDAddrNode->getOperand(1);
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// We want to find the pattern global_addr + offset
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SDNode *OP1N = OP1.getNode();
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if (OP1N->getOpcode() <= ISD::BUILTIN_OP_END || OP1N->getNumOperands() == 0)
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return;
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DEBUG(dbgs() << "Check candidate load: "; LD->dump(); dbgs() << '\n');
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const GlobalAddressSDNode *GADN =
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dyn_cast<GlobalAddressSDNode>(OP1N->getOperand(0).getNode());
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const ConstantSDNode *CDN = dyn_cast<ConstantSDNode>(OP2.getNode());
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if (GADN && CDN)
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to_replace =
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getConstantFieldValue(GADN, CDN->getZExtValue(), size, new_val.c);
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} else if (LDAddrNode->getOpcode() > ISD::BUILTIN_OP_END &&
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LDAddrNode->getNumOperands() > 0) {
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DEBUG(dbgs() << "Check candidate load: "; LD->dump(); dbgs() << '\n');
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SDValue OP1 = LDAddrNode->getOperand(0);
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if (const GlobalAddressSDNode *GADN =
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dyn_cast<GlobalAddressSDNode>(OP1.getNode()))
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to_replace = getConstantFieldValue(GADN, 0, size, new_val.c);
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}
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if (!to_replace)
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return;
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// replacing the old with a new value
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uint64_t val;
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if (size == 1)
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val = new_val.c[0];
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else if (size == 2)
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val = new_val.s;
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else if (size == 4)
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val = new_val.i;
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else {
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val = new_val.d;
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}
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DEBUG(dbgs() << "Replacing load of size " << size << " with constant " << val
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<< '\n');
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SDValue NVal = CurDAG->getConstant(val, DL, MVT::i64);
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// After replacement, the current node is dead, we need to
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// go backward one step to make iterator still work
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I--;
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SDValue From[] = {SDValue(Node, 0), SDValue(Node, 1)};
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SDValue To[] = {NVal, NVal};
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CurDAG->ReplaceAllUsesOfValuesWith(From, To, 2);
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I++;
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// It is safe to delete node now
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CurDAG->DeleteNode(Node);
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}
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void BPFDAGToDAGISel::PreprocessISelDAG() {
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// Iterate through all nodes, only interested in loads from ConstantStruct
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// ConstantArray should have converted by IR->DAG processing
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// Iterate through all nodes, interested in the following cases:
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//
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// . loads from ConstantStruct or ConstantArray of constructs
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// which can be turns into constant itself, with this we can
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// avoid reading from read-only section at runtime.
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//
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// . reg truncating is often the result of 8/16/32bit->64bit or
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// 8/16bit->32bit conversion. If the reg value is loaded with
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// masked byte width, the AND operation can be removed since
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// BPF LOAD already has zero extension.
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//
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// This also solved a correctness issue.
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// In BPF socket-related program, e.g., __sk_buff->{data, data_end}
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// are 32-bit registers, but later on, kernel verifier will rewrite
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// it with 64-bit value. Therefore, truncating the value after the
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// load will result in incorrect code.
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for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
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E = CurDAG->allnodes_end();
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I != E;) {
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SDNode *Node = &*I++;
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unsigned Opcode = Node->getOpcode();
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if (Opcode != ISD::LOAD)
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continue;
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union {
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uint8_t c[8];
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uint16_t s;
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uint32_t i;
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uint64_t d;
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} new_val; // hold up the constant values replacing loads.
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bool to_replace = false;
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SDLoc DL(Node);
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const LoadSDNode *LD = cast<LoadSDNode>(Node);
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uint64_t size = LD->getMemOperand()->getSize();
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if (!size || size > 8 || (size & (size - 1)))
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continue;
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SDNode *LDAddrNode = LD->getOperand(1).getNode();
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// Match LDAddr against either global_addr or (global_addr + offset)
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unsigned opcode = LDAddrNode->getOpcode();
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if (opcode == ISD::ADD) {
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SDValue OP1 = LDAddrNode->getOperand(0);
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SDValue OP2 = LDAddrNode->getOperand(1);
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// We want to find the pattern global_addr + offset
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SDNode *OP1N = OP1.getNode();
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if (OP1N->getOpcode() <= ISD::BUILTIN_OP_END ||
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OP1N->getNumOperands() == 0)
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continue;
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DEBUG(dbgs() << "Check candidate load: "; LD->dump(); dbgs() << '\n');
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const GlobalAddressSDNode *GADN =
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dyn_cast<GlobalAddressSDNode>(OP1N->getOperand(0).getNode());
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const ConstantSDNode *CDN = dyn_cast<ConstantSDNode>(OP2.getNode());
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if (GADN && CDN)
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to_replace =
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getConstantFieldValue(GADN, CDN->getZExtValue(), size, new_val.c);
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} else if (LDAddrNode->getOpcode() > ISD::BUILTIN_OP_END &&
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LDAddrNode->getNumOperands() > 0) {
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DEBUG(dbgs() << "Check candidate load: "; LD->dump(); dbgs() << '\n');
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SDValue OP1 = LDAddrNode->getOperand(0);
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if (const GlobalAddressSDNode *GADN =
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dyn_cast<GlobalAddressSDNode>(OP1.getNode()))
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to_replace = getConstantFieldValue(GADN, 0, size, new_val.c);
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}
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if (!to_replace)
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continue;
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// replacing the old with a new value
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uint64_t val;
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if (size == 1)
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val = new_val.c[0];
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else if (size == 2)
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val = new_val.s;
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else if (size == 4)
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val = new_val.i;
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else {
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val = new_val.d;
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}
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DEBUG(dbgs() << "Replacing load of size " << size << " with constant "
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<< val << '\n');
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SDValue NVal = CurDAG->getConstant(val, DL, MVT::i64);
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// After replacement, the current node is dead, we need to
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// go backward one step to make iterator still work
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I--;
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SDValue From[] = {SDValue(Node, 0), SDValue(Node, 1)};
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SDValue To[] = {NVal, NVal};
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CurDAG->ReplaceAllUsesOfValuesWith(From, To, 2);
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I++;
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// It is safe to delete node now
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CurDAG->DeleteNode(Node);
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if (Opcode == ISD::LOAD)
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PreprocessLoad(Node, I);
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else if (Opcode == ISD::CopyToReg)
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PreprocessCopyToReg(Node);
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else if (Opcode == ISD::AND)
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PreprocessTrunc(Node, I);
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}
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}
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@ -415,6 +445,134 @@ bool BPFDAGToDAGISel::fillConstantStruct(const DataLayout &DL,
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return true;
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}
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void BPFDAGToDAGISel::PreprocessCopyToReg(SDNode *Node) {
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const RegisterSDNode *RegN = dyn_cast<RegisterSDNode>(Node->getOperand(1));
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if (!RegN || !TargetRegisterInfo::isVirtualRegister(RegN->getReg()))
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return;
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const LoadSDNode *LD = dyn_cast<LoadSDNode>(Node->getOperand(2));
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if (!LD)
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return;
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// Assign a load value to a virtual register. record its load width
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unsigned mem_load_op = 0;
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switch (LD->getMemOperand()->getSize()) {
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default:
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return;
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case 4:
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mem_load_op = BPF::LDW;
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break;
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case 2:
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mem_load_op = BPF::LDH;
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break;
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case 1:
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mem_load_op = BPF::LDB;
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break;
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}
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DEBUG(dbgs() << "Find Load Value to VReg "
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<< TargetRegisterInfo::virtReg2Index(RegN->getReg()) << '\n');
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load_to_vreg_[RegN->getReg()] = mem_load_op;
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}
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void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node,
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SelectionDAG::allnodes_iterator I) {
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ConstantSDNode *MaskN = dyn_cast<ConstantSDNode>(Node->getOperand(1));
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if (!MaskN)
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return;
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unsigned match_load_op = 0;
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switch (MaskN->getZExtValue()) {
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default:
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return;
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case 0xFFFFFFFF:
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match_load_op = BPF::LDW;
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break;
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case 0xFFFF:
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match_load_op = BPF::LDH;
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break;
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case 0xFF:
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match_load_op = BPF::LDB;
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break;
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}
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// The Reg operand should be a virtual register, which is defined
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// outside the current basic block. DAG combiner has done a pretty
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// good job in removing truncating inside a single basic block.
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SDValue BaseV = Node->getOperand(0);
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if (BaseV.getOpcode() != ISD::CopyFromReg)
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return;
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const RegisterSDNode *RegN =
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dyn_cast<RegisterSDNode>(BaseV.getNode()->getOperand(1));
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if (!RegN || !TargetRegisterInfo::isVirtualRegister(RegN->getReg()))
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return;
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unsigned AndOpReg = RegN->getReg();
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DEBUG(dbgs() << "Examine %vreg" << TargetRegisterInfo::virtReg2Index(AndOpReg)
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<< '\n');
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// Examine the PHI insns in the MachineBasicBlock to found out the
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// definitions of this virtual register. At this stage (DAG2DAG
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// transformation), only PHI machine insns are available in the machine basic
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// block.
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MachineBasicBlock *MBB = FuncInfo->MBB;
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MachineInstr *MII = nullptr;
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for (auto &MI : *MBB) {
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for (unsigned i = 0; i < MI.getNumOperands(); ++i) {
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const MachineOperand &MOP = MI.getOperand(i);
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if (!MOP.isReg() || !MOP.isDef())
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continue;
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unsigned Reg = MOP.getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg) && Reg == AndOpReg) {
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MII = &MI;
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break;
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}
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}
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}
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if (MII == nullptr) {
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// No phi definition in this block.
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if (!checkLoadDef(AndOpReg, match_load_op))
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return;
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} else {
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// The PHI node looks like:
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// %vreg2<def> = PHI %vreg0, <BB#1>, %vreg1, <BB#3>
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// Trace each incoming definition, e.g., (%vreg0, BB#1) and (%vreg1, BB#3)
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// The AND operation can be removed if both %vreg0 in BB#1 and %vreg1 in
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// BB#3 are defined with with a load matching the MaskN.
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DEBUG(dbgs() << "Check PHI Insn: "; MII->dump(); dbgs() << '\n');
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unsigned PrevReg = -1;
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for (unsigned i = 0; i < MII->getNumOperands(); ++i) {
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const MachineOperand &MOP = MII->getOperand(i);
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if (MOP.isReg()) {
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if (MOP.isDef())
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continue;
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PrevReg = MOP.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(PrevReg))
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return;
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if (!checkLoadDef(PrevReg, match_load_op))
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return;
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}
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}
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}
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DEBUG(dbgs() << "Remove the redundant AND operation in: "; Node->dump();
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dbgs() << '\n');
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I--;
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CurDAG->ReplaceAllUsesWith(SDValue(Node, 0), BaseV);
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I++;
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CurDAG->DeleteNode(Node);
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}
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bool BPFDAGToDAGISel::checkLoadDef(unsigned DefReg, unsigned match_load_op) {
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auto it = load_to_vreg_.find(DefReg);
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if (it == load_to_vreg_.end())
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return false; // The definition of register is not exported yet.
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return it->second == match_load_op;
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}
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FunctionPass *llvm::createBPFISelDag(BPFTargetMachine &TM) {
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return new BPFDAGToDAGISel(TM);
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}
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@ -0,0 +1,87 @@
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; RUN: llc < %s -march=bpf -verify-machineinstrs | FileCheck %s
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; Source code:
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; struct xdp_md {
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; unsigned data;
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; unsigned data_end;
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; };
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;
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; int gbl;
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; int xdp_dummy(struct xdp_md *xdp)
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; {
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; char tmp;
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; long addr;
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;
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; if (gbl) {
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; long addr1 = (long)xdp->data;
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; tmp = *(char *)addr1;
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; if (tmp == 1)
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; return 3;
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; } else {
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; tmp = *(volatile char *)(long)xdp->data_end;
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; if (tmp == 1)
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; return 2;
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; }
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; addr = (long)xdp->data;
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; tmp = *(volatile char *)addr;
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; if (tmp == 0)
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; return 1;
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; return 0;
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; }
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%struct.xdp_md = type { i32, i32 }
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@gbl = common local_unnamed_addr global i32 0, align 4
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; Function Attrs: norecurse nounwind
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define i32 @xdp_dummy(%struct.xdp_md* nocapture readonly %xdp) local_unnamed_addr #0 {
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entry:
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%0 = load i32, i32* @gbl, align 4
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%tobool = icmp eq i32 %0, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%data = getelementptr inbounds %struct.xdp_md, %struct.xdp_md* %xdp, i64 0, i32 0
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%1 = load i32, i32* %data, align 4
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%conv = zext i32 %1 to i64
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%2 = inttoptr i64 %conv to i8*
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%3 = load i8, i8* %2, align 1
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%cmp = icmp eq i8 %3, 1
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br i1 %cmp, label %cleanup20, label %if.end12
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; CHECK: r1 = *(u32 *)(r1 + 0)
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; CHECK: r2 = *(u8 *)(r1 + 0)
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if.else: ; preds = %entry
|
||||
%data_end = getelementptr inbounds %struct.xdp_md, %struct.xdp_md* %xdp, i64 0, i32 1
|
||||
%4 = load i32, i32* %data_end, align 4
|
||||
%conv6 = zext i32 %4 to i64
|
||||
; CHECK: r2 = *(u32 *)(r1 + 4)
|
||||
%5 = inttoptr i64 %conv6 to i8*
|
||||
%6 = load volatile i8, i8* %5, align 1
|
||||
%cmp8 = icmp eq i8 %6, 1
|
||||
br i1 %cmp8, label %cleanup20, label %if.else.if.end12_crit_edge
|
||||
|
||||
if.else.if.end12_crit_edge: ; preds = %if.else
|
||||
%data13.phi.trans.insert = getelementptr inbounds %struct.xdp_md, %struct.xdp_md* %xdp, i64 0, i32 0
|
||||
%.pre = load i32, i32* %data13.phi.trans.insert, align 4
|
||||
br label %if.end12
|
||||
; CHECK: r1 = *(u32 *)(r1 + 0)
|
||||
|
||||
if.end12: ; preds = %if.else.if.end12_crit_edge, %if.then
|
||||
%7 = phi i32 [ %.pre, %if.else.if.end12_crit_edge ], [ %1, %if.then ]
|
||||
%conv14 = zext i32 %7 to i64
|
||||
; CHECK-NOT: r1 <<= 32
|
||||
; CHECK-NOT: r1 >>= 32
|
||||
%8 = inttoptr i64 %conv14 to i8*
|
||||
%9 = load volatile i8, i8* %8, align 1
|
||||
; CHECK: r1 = *(u8 *)(r1 + 0)
|
||||
%cmp16 = icmp eq i8 %9, 0
|
||||
%.28 = zext i1 %cmp16 to i32
|
||||
br label %cleanup20
|
||||
|
||||
cleanup20: ; preds = %if.then, %if.end12, %if.else
|
||||
%retval.1 = phi i32 [ 3, %if.then ], [ 2, %if.else ], [ %.28, %if.end12 ]
|
||||
ret i32 %retval.1
|
||||
}
|
||||
|
||||
attributes #0 = { norecurse nounwind }
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
; RUN: llc < %s -march=bpf -verify-machineinstrs | FileCheck %s
|
||||
|
||||
; Source code:
|
||||
; struct xdp_md {
|
||||
; unsigned data;
|
||||
; unsigned data_end;
|
||||
; };
|
||||
;
|
||||
; int gbl;
|
||||
; int xdp_dummy(struct xdp_md *xdp)
|
||||
; {
|
||||
; char addr = *(char *)(long)xdp->data;
|
||||
; if (gbl) {
|
||||
; if (gbl == 1)
|
||||
; return 1;
|
||||
; if (addr == 1)
|
||||
; return 3;
|
||||
; } else if (addr == 0)
|
||||
; return 2;
|
||||
; return 0;
|
||||
; }
|
||||
|
||||
%struct.xdp_md = type { i32, i32 }
|
||||
|
||||
@gbl = common local_unnamed_addr global i32 0, align 4
|
||||
|
||||
; Function Attrs: norecurse nounwind readonly
|
||||
define i32 @xdp_dummy(%struct.xdp_md* nocapture readonly %xdp) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%data = getelementptr inbounds %struct.xdp_md, %struct.xdp_md* %xdp, i64 0, i32 0
|
||||
%0 = load i32, i32* %data, align 4
|
||||
%conv = zext i32 %0 to i64
|
||||
%1 = inttoptr i64 %conv to i8*
|
||||
%2 = load i8, i8* %1, align 1
|
||||
; CHECK: r1 = *(u32 *)(r1 + 0)
|
||||
; CHECK: r1 = *(u8 *)(r1 + 0)
|
||||
%3 = load i32, i32* @gbl, align 4
|
||||
switch i32 %3, label %if.end [
|
||||
i32 0, label %if.else
|
||||
i32 1, label %cleanup
|
||||
]
|
||||
|
||||
if.end: ; preds = %entry
|
||||
%cmp4 = icmp eq i8 %2, 1
|
||||
; CHECK: r0 = 3
|
||||
; CHECK-NOT: r1 &= 255
|
||||
; CHECK: if r1 == 1 goto
|
||||
br i1 %cmp4, label %cleanup, label %if.end13
|
||||
|
||||
if.else: ; preds = %entry
|
||||
%cmp9 = icmp eq i8 %2, 0
|
||||
; CHECK: r0 = 2
|
||||
; CHECK-NOT: r1 &= 255
|
||||
; CHECK: if r1 == 0 goto
|
||||
br i1 %cmp9, label %cleanup, label %if.end13
|
||||
|
||||
if.end13: ; preds = %if.else, %if.end
|
||||
br label %cleanup
|
||||
|
||||
cleanup: ; preds = %if.else, %if.end, %entry, %if.end13
|
||||
%retval.0 = phi i32 [ 0, %if.end13 ], [ 1, %entry ], [ 3, %if.end ], [ 2, %if.else ]
|
||||
ret i32 %retval.0
|
||||
}
|
||||
|
||||
attributes #0 = { norecurse nounwind readonly }
|
||||
Loading…
Reference in New Issue