forked from OSchip/llvm-project
[X86] Give the AVX512 VEXTRACT instructions the same SchedRWs as the SSE/AVX versions.
llvm-svn: 328958
This commit is contained in:
Craig Topper
parent
7a4f647dc2
commit
5fb1dc2d22
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@ -799,7 +799,7 @@ multiclass vextract_for_size_split<int Opcode,
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X86VectorVTInfo From, X86VectorVTInfo To,
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SDPatternOperator vextract_extract,
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SDPatternOperator vextract_for_mask,
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OpndItins itins> {
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SchedWrite SchedRR, SchedWrite SchedMR> {
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let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
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defm rr : AVX512_maskable_split<Opcode, MRMDestReg, To, (outs To.RC:$dst),
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@ -808,7 +808,7 @@ multiclass vextract_for_size_split<int Opcode,
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"$idx, $src1", "$src1, $idx",
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(vextract_extract:$idx (From.VT From.RC:$src1), (iPTR imm)),
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(vextract_for_mask:$idx (From.VT From.RC:$src1), (iPTR imm)),
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itins.rr>, AVX512AIi8Base, EVEX, Sched<[itins.Sched]>;
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NoItinerary>, AVX512AIi8Base, EVEX, Sched<[SchedRR]>;
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def mr : AVX512AIi8<Opcode, MRMDestMem, (outs),
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(ins To.MemOp:$dst, From.RC:$src1, u8imm:$idx),
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@ -816,8 +816,8 @@ multiclass vextract_for_size_split<int Opcode,
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"\t{$idx, $src1, $dst|$dst, $src1, $idx}",
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[(store (To.VT (vextract_extract:$idx
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(From.VT From.RC:$src1), (iPTR imm))),
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addr:$dst)], itins.rm>, EVEX,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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addr:$dst)], NoItinerary>, EVEX,
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Sched<[SchedMR]>;
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let mayStore = 1, hasSideEffects = 0 in
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def mrk : AVX512AIi8<Opcode, MRMDestMem, (outs),
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@ -826,8 +826,8 @@ multiclass vextract_for_size_split<int Opcode,
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"vextract" # To.EltTypeName # "x" # To.NumElts #
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"\t{$idx, $src1, $dst {${mask}}|"
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"$dst {${mask}}, $src1, $idx}",
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[], itins.rm>, EVEX_K, EVEX,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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[], NoItinerary>, EVEX_K, EVEX,
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Sched<[SchedMR]>;
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}
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}
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@ -835,8 +835,8 @@ multiclass vextract_for_size_split<int Opcode,
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multiclass vextract_for_size<int Opcode, X86VectorVTInfo From,
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X86VectorVTInfo To,
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SDPatternOperator vextract_extract,
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OpndItins itins> :
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vextract_for_size_split<Opcode, From, To, vextract_extract, vextract_extract, itins>;
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SchedWrite SchedRR, SchedWrite SchedMR> :
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vextract_for_size_split<Opcode, From, To, vextract_extract, vextract_extract, SchedRR, SchedMR>;
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// Codegen pattern for the alternative types
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multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
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@ -856,24 +856,24 @@ multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
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multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
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ValueType EltVT64, int Opcode256,
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OpndItins itins> {
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SchedWrite SchedRR, SchedWrite SchedMR> {
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let Predicates = [HasAVX512] in {
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defm NAME # "32x4Z" : vextract_for_size<Opcode128,
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X86VectorVTInfo<16, EltVT32, VR512>,
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X86VectorVTInfo< 4, EltVT32, VR128X>,
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vextract128_extract, itins>,
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vextract128_extract, SchedRR, SchedMR>,
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EVEX_V512, EVEX_CD8<32, CD8VT4>;
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defm NAME # "64x4Z" : vextract_for_size<Opcode256,
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X86VectorVTInfo< 8, EltVT64, VR512>,
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X86VectorVTInfo< 4, EltVT64, VR256X>,
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vextract256_extract, itins>,
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vextract256_extract, SchedRR, SchedMR>,
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VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
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}
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let Predicates = [HasVLX] in
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defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
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X86VectorVTInfo< 8, EltVT32, VR256X>,
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X86VectorVTInfo< 4, EltVT32, VR128X>,
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vextract128_extract, itins>,
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vextract128_extract, SchedRR, SchedMR>,
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EVEX_V256, EVEX_CD8<32, CD8VT4>;
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// Even with DQI we'd like to only use these instructions for masking.
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@ -881,7 +881,7 @@ multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
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defm NAME # "64x2Z256" : vextract_for_size_split<Opcode128,
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X86VectorVTInfo< 4, EltVT64, VR256X>,
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X86VectorVTInfo< 2, EltVT64, VR128X>,
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null_frag, vextract128_extract, itins>,
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null_frag, vextract128_extract, SchedRR, SchedMR>,
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VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
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// Even with DQI we'd like to only use these instructions for masking.
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@ -889,28 +889,18 @@ multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
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defm NAME # "64x2Z" : vextract_for_size_split<Opcode128,
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X86VectorVTInfo< 8, EltVT64, VR512>,
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X86VectorVTInfo< 2, EltVT64, VR128X>,
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null_frag, vextract128_extract, itins>,
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null_frag, vextract128_extract, SchedRR, SchedMR>,
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VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
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defm NAME # "32x8Z" : vextract_for_size_split<Opcode256,
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X86VectorVTInfo<16, EltVT32, VR512>,
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X86VectorVTInfo< 8, EltVT32, VR256X>,
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null_frag, vextract256_extract, itins>,
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null_frag, vextract256_extract, SchedRR, SchedMR>,
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EVEX_V512, EVEX_CD8<32, CD8VT8>;
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}
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}
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// FIXME: Is there a better scheduler itinerary for VEXTRACTF/VEXTRACTI?
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let Sched = WriteFShuffle256 in
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def AVX512_VEXTRACTF : OpndItins<
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IIC_SSE_SHUFP, IIC_SSE_SHUFP
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>;
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let Sched = WriteShuffle256 in
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def AVX512_VEXTRACTI : OpndItins<
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IIC_SSE_PSHUF_RI, IIC_SSE_PSHUF_MI
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>;
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defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b, AVX512_VEXTRACTF>;
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defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b, AVX512_VEXTRACTI>;
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defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b, WriteFShuffle256, WriteFStore>;
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defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b, WriteShuffle256, WriteVecStore>;
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// extract_subvector codegen patterns with the alternative types.
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// Even with AVX512DQ we'll still use these for unmasked operations.
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@ -1117,14 +1107,14 @@ def VEXTRACTPSZrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
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(ins VR128X:$src1, u8imm:$src2),
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"vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))],
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IIC_SSE_EXTRACTPS_RR>, EVEX, VEX_WIG, Sched<[WriteFShuffle]>;
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IIC_SSE_EXTRACTPS_RR>, EVEX, VEX_WIG, Sched<[WriteFBlend]>;
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def VEXTRACTPSZmr : AVX512AIi8<0x17, MRMDestMem, (outs),
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(ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
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"vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
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addr:$dst)], IIC_SSE_EXTRACTPS_RM>,
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EVEX, VEX_WIG, EVEX_CD8<32, CD8VT1>, Sched<[WriteFShuffleLd]>;
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EVEX, VEX_WIG, EVEX_CD8<32, CD8VT1>, Sched<[WriteFBlendLd, WriteRMW]>;
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//===---------------------------------------------------------------------===//
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// AVX-512 BROADCAST
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