forked from OSchip/llvm-project
[RISCV] Use multiclass inheritance to simplify some of riscv_vector.td. NFCI
We don't need to instantiate single multiclasses inside of other multiclasses. We can use inheritance and save writing 'defm ""'. Reviewed By: khchen Differential Revision: https://reviews.llvm.org/D100074
This commit is contained in:
Craig Topper
parent
d9065fe8ea
commit
5f6b3d1833
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@ -217,127 +217,109 @@ multiclass RVVBuiltinSet<string intrinsic_name, string type_range,
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// IntrinsicTypes is output, op0, op1 [-1, 0, 1]
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multiclass RVVOutOp0Op1BuiltinSet<string intrinsic_name, string type_range,
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list<list<string>> suffixes_prototypes> {
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defm NAME : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes,
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list<list<string>> suffixes_prototypes>
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: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes,
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[-1, 0, 1]>;
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}
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// IntrinsicTypes is output, op1 [-1, 1]
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multiclass RVVOutOp1BuiltinSet<string intrinsic_name, string type_range,
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list<list<string>> suffixes_prototypes> {
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defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1]>;
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}
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list<list<string>> suffixes_prototypes>
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: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1]>;
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multiclass RVVOp0Op1BuiltinSet<string intrinsic_name, string type_range,
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list<list<string>> suffixes_prototypes> {
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defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [0, 1]>;
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}
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list<list<string>> suffixes_prototypes>
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: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [0, 1]>;
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multiclass RVVOutOp1Op2BuiltinSet<string intrinsic_name, string type_range,
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list<list<string>> suffixes_prototypes> {
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defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1, 2]>;
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}
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list<list<string>> suffixes_prototypes>
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: RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1, 2]>;
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multiclass RVVSignedBinBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "v", "vvv"],
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["vx", "v", "vve"]]>;
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}
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multiclass RVVSignedBinBuiltinSet
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: RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "v", "vvv"],
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["vx", "v", "vve"]]>;
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multiclass RVVUnsignedBinBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "Uv", "UvUvUv"],
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["vx", "Uv", "UvUvUe"]]>;
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}
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multiclass RVVUnsignedBinBuiltinSet
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: RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "Uv", "UvUvUv"],
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["vx", "Uv", "UvUvUe"]]>;
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multiclass RVVIntBinBuiltinSet {
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defm "" : RVVSignedBinBuiltinSet;
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defm "" : RVVUnsignedBinBuiltinSet;
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}
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multiclass RVVIntBinBuiltinSet
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: RVVSignedBinBuiltinSet,
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RVVUnsignedBinBuiltinSet;
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multiclass RVVSignedShiftBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "v", "vvUv"],
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["vx", "v", "vvz"]]>;
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}
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multiclass RVVSignedShiftBuiltinSet
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: RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "v", "vvUv"],
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["vx", "v", "vvz"]]>;
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multiclass RVVUnsignedShiftBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "Uv", "UvUvUv"],
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["vx", "Uv", "UvUvz"]]>;
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}
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multiclass RVVUnsignedShiftBuiltinSet
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: RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "Uv", "UvUvUv"],
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["vx", "Uv", "UvUvz"]]>;
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multiclass RVVShiftBuiltinSet {
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defm "" : RVVSignedShiftBuiltinSet;
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defm "" : RVVUnsignedShiftBuiltinSet;
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}
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multiclass RVVShiftBuiltinSet
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: RVVSignedShiftBuiltinSet,
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RVVUnsignedShiftBuiltinSet;
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let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
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multiclass RVVSignedNShiftBuiltinSet {
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defm "" : RVVOutOp0Op1BuiltinSet<NAME, "csil",
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multiclass RVVSignedNShiftBuiltinSet
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: RVVOutOp0Op1BuiltinSet<NAME, "csil",
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[["wv", "v", "vwUv"],
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["wx", "v", "vwz"]]>;
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}
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multiclass RVVUnsignedNShiftBuiltinSet {
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defm "" : RVVOutOp0Op1BuiltinSet<NAME, "csil",
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multiclass RVVUnsignedNShiftBuiltinSet
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: RVVOutOp0Op1BuiltinSet<NAME, "csil",
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[["wv", "Uv", "UvUwUv"],
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["wx", "Uv", "UvUwz"]]>;
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}
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}
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multiclass RVVIntTerBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "v", "vvvv"],
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["vx", "v", "vvev"],
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["vv", "Uv", "UvUvUvUv"],
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["vx", "Uv", "UvUvUeUv"]]>;
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}
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multiclass RVVIntTerBuiltinSet
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: RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "v", "vvvv"],
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["vx", "v", "vvev"],
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["vv", "Uv", "UvUvUvUv"],
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["vx", "Uv", "UvUvUeUv"]]>;
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multiclass RVVCarryinBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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[["vvm", "v", "vvvm"],
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["vxm", "v", "vvem"],
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["vvm", "Uv", "UvUvUvm"],
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["vxm", "Uv", "UvUvUem"]]>;
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}
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multiclass RVVCarryinBuiltinSet
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: RVVOutOp1BuiltinSet<NAME, "csil",
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[["vvm", "v", "vvvm"],
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["vxm", "v", "vvem"],
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["vvm", "Uv", "UvUvUvm"],
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["vxm", "Uv", "UvUvUem"]]>;
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multiclass RVVCarryOutInBuiltinSet<string intrinsic_name> {
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defm "" : RVVOp0Op1BuiltinSet<intrinsic_name, "csil",
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[["vvm", "vm", "mvvm"],
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["vxm", "vm", "mvem"],
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["vvm", "Uvm", "mUvUvm"],
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["vxm", "Uvm", "mUvUem"]]>;
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}
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multiclass RVVCarryOutInBuiltinSet<string intrinsic_name>
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: RVVOp0Op1BuiltinSet<intrinsic_name, "csil",
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[["vvm", "vm", "mvvm"],
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["vxm", "vm", "mvem"],
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["vvm", "Uvm", "mUvUvm"],
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["vxm", "Uvm", "mUvUem"]]>;
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multiclass RVVSignedMaskOutBuiltinSet {
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defm "" : RVVOp0Op1BuiltinSet<NAME, "csil",
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[["vv", "vm", "mvv"],
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["vx", "vm", "mve"]]>;
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}
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multiclass RVVSignedMaskOutBuiltinSet
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: RVVOp0Op1BuiltinSet<NAME, "csil",
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[["vv", "vm", "mvv"],
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["vx", "vm", "mve"]]>;
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multiclass RVVUnsignedMaskOutBuiltinSet {
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defm "" : RVVOp0Op1BuiltinSet<NAME, "csil",
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[["vv", "Uvm", "mUvUv"],
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["vx", "Uvm", "mUvUe"]]>;
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}
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multiclass RVVUnsignedMaskOutBuiltinSet
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: RVVOp0Op1BuiltinSet<NAME, "csil",
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[["vv", "Uvm", "mUvUv"],
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["vx", "Uvm", "mUvUe"]]>;
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multiclass RVVIntMaskOutBuiltinSet {
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defm "" : RVVSignedMaskOutBuiltinSet;
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defm "" : RVVUnsignedMaskOutBuiltinSet;
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}
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multiclass RVVIntMaskOutBuiltinSet
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: RVVSignedMaskOutBuiltinSet,
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RVVUnsignedMaskOutBuiltinSet;
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multiclass RVVFloatingBinBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "fd",
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[["vv", "v", "vvv"],
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["vf", "v", "vve"]]>;
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}
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multiclass RVVFloatingBinBuiltinSet
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: RVVOutOp1BuiltinSet<NAME, "fd",
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[["vv", "v", "vvv"],
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["vf", "v", "vve"]]>;
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multiclass RVVIntExt<string intrinsic_name, string suffix, string prototype,
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string type_range> {
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let IRName = intrinsic_name, IRNameMask = intrinsic_name # "_mask",
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MangledName = NAME, IntrinsicTypes = [-1, 0] in {
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def "" : RVVBuiltin<suffix, prototype, type_range>;
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}
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class RVVIntExt<string intrinsic_name, string suffix, string prototype,
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string type_range>
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: RVVBuiltin<suffix, prototype, type_range> {
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let IRName = intrinsic_name;
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let IRNameMask = intrinsic_name # "_mask";
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let MangledName = NAME;
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let IntrinsicTypes = [-1, 0];
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}
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defvar TypeList = ["c","s","i","l","f","d"];
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@ -520,16 +502,16 @@ defm vrsub : RVVOutOp1BuiltinSet<"vrsub", "csil",
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// 12.3. Vector Integer Extension
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let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
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defm vsext_vf2 : RVVIntExt<"vsext", "w", "wv", "csi">;
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defm vzext_vf2 : RVVIntExt<"vzext", "Uw", "UwUv", "csi">;
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def vsext_vf2 : RVVIntExt<"vsext", "w", "wv", "csi">;
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def vzext_vf2 : RVVIntExt<"vzext", "Uw", "UwUv", "csi">;
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}
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let Log2LMUL = [-3, -2, -1, 0, 1] in {
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defm vsext_vf4 : RVVIntExt<"vsext", "q", "qv", "cs">;
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defm vzext_vf4 : RVVIntExt<"vzext", "Uq", "UqUv", "cs">;
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def vsext_vf4 : RVVIntExt<"vsext", "q", "qv", "cs">;
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def vzext_vf4 : RVVIntExt<"vzext", "Uq", "UqUv", "cs">;
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}
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let Log2LMUL = [-3, -2, -1, 0] in {
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defm vsext_vf8 : RVVIntExt<"vsext", "o", "ov", "c">;
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defm vzext_vf8 : RVVIntExt<"vzext", "Uo", "UoUv", "c">;
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def vsext_vf8 : RVVIntExt<"vsext", "o", "ov", "c">;
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def vzext_vf8 : RVVIntExt<"vzext", "Uo", "UoUv", "c">;
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}
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// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
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