forked from OSchip/llvm-project
[ARM] Tests for tail predicated loads. NFC
This commit is contained in:
David Green
parent
fef2607124
commit
5f45f91de4
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv8.1m.main -mattr=+mve -tail-predication=enabled --verify-machineinstrs %s -o - | FileCheck %s
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define void @arm_cmplx_mag_squared_q15_mve(i16* %pSrc, i16* %pDst, i32 %blockSize) {
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; CHECK-LABEL: arm_cmplx_mag_squared_q15_mve:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: subs.w r12, r2, #8
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; CHECK-NEXT: mov.w r3, #-1
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; CHECK-NEXT: csinv r3, r3, r12, pl
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; CHECK-NEXT: add.w r12, r3, r2
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; CHECK-NEXT: movs r3, #1
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; CHECK-NEXT: add.w lr, r3, r12, lsr #3
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB0_1: @ %do.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vld20.16 {q0, q1}, [r0]
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; CHECK-NEXT: vctp.16 r2
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; CHECK-NEXT: subs r2, #8
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; CHECK-NEXT: vld21.16 {q0, q1}, [r0]!
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; CHECK-NEXT: vpstttt
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; CHECK-NEXT: vmulht.s16 q2, q1, q1
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; CHECK-NEXT: vmulht.s16 q0, q0, q0
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; CHECK-NEXT: vqaddt.s16 q0, q0, q2
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; CHECK-NEXT: vshrt.s16 q0, q0, #1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vstrht.16 q0, [r1], #16
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; CHECK-NEXT: le lr, .LBB0_1
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; CHECK-NEXT: @ %bb.2: @ %do.end
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; CHECK-NEXT: pop {r7, pc}
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entry:
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%blockSize.addr.0 = phi i32 [ %blockSize, %entry ], [ %sub, %do.body ]
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%pDst.addr.0 = phi i16* [ %pDst, %entry ], [ %add.ptr7, %do.body ]
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%pSrc.addr.0 = phi i16* [ %pSrc, %entry ], [ %add.ptr, %do.body ]
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%0 = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %blockSize.addr.0)
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%1 = tail call { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0i16(i16* %pSrc.addr.0)
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%2 = extractvalue { <8 x i16>, <8 x i16> } %1, 0
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%3 = extractvalue { <8 x i16>, <8 x i16> } %1, 1
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%4 = tail call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %2, <8 x i16> %2, i32 0, <8 x i1> %0, <8 x i16> undef)
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%5 = tail call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %3, <8 x i16> %3, i32 0, <8 x i1> %0, <8 x i16> undef)
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%6 = tail call <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16> %4, <8 x i16> %5, i32 0, <8 x i1> %0, <8 x i16> undef)
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%7 = tail call <8 x i16> @llvm.arm.mve.shr.imm.predicated.v8i16.v8i1(<8 x i16> %6, i32 1, i32 0, <8 x i1> %0, <8 x i16> undef)
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%8 = bitcast i16* %pDst.addr.0 to <8 x i16>*
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tail call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %7, <8 x i16>* %8, i32 2, <8 x i1> %0)
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%add.ptr = getelementptr inbounds i16, i16* %pSrc.addr.0, i32 16
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%add.ptr7 = getelementptr inbounds i16, i16* %pDst.addr.0, i32 8
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%sub = add i32 %blockSize.addr.0, -8
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%cmp = icmp sgt i32 %sub, 0
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br i1 %cmp, label %do.body, label %do.end
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do.end: ; preds = %do.body
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ret void
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}
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define i32 @bad(i32* readonly %x, i32* nocapture readonly %y, i32 %n) {
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; CHECK-LABEL: bad:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: mov r3, r2
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; CHECK-NEXT: cmp r2, #4
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; CHECK-NEXT: it ge
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; CHECK-NEXT: movge r3, #4
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; CHECK-NEXT: subs r3, r2, r3
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; CHECK-NEXT: add.w r12, r3, #3
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; CHECK-NEXT: movs r3, #1
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; CHECK-NEXT: add.w lr, r3, r12, lsr #2
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB1_1: @ %do.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vctp.32 r2
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vldrwt.u32 q0, [r0], #16
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; CHECK-NEXT: vldrw.u32 q1, [r1], #16
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; CHECK-NEXT: subs r2, #4
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; CHECK-NEXT: vmlava.s32 r12, q0, q1
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; CHECK-NEXT: le lr, .LBB1_1
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; CHECK-NEXT: @ %bb.2: @ %do.end
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: pop {r7, pc}
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entry:
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%s.0 = phi i32 [ 0, %entry ], [ %5, %do.body ]
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%n.addr.0 = phi i32 [ %n, %entry ], [ %sub, %do.body ]
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%y.addr.0 = phi i32* [ %y, %entry ], [ %add.ptr1, %do.body ]
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%x.addr.0 = phi i32* [ %x, %entry ], [ %add.ptr, %do.body ]
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%0 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.0)
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%1 = bitcast i32* %x.addr.0 to <4 x i32>*
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%2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %0, <4 x i32> zeroinitializer)
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%add.ptr = getelementptr inbounds i32, i32* %x.addr.0, i32 4
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%3 = bitcast i32* %y.addr.0 to <4 x i32>*
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%4 = load <4 x i32>, <4 x i32>* %3, align 4
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%add.ptr1 = getelementptr inbounds i32, i32* %y.addr.0, i32 4
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%5 = tail call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %s.0, <4 x i32> %2, <4 x i32> %4)
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%sub = add nsw i32 %n.addr.0, -4
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%cmp = icmp sgt i32 %n.addr.0, 4
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br i1 %cmp, label %do.body, label %do.end
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do.end: ; preds = %do.body
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ret i32 %5
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}
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define i32 @good(i32* readonly %x, i32* readonly %y, i32 %n) {
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; CHECK-LABEL: good:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: dlstp.32 lr, r2
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; CHECK-NEXT: .LBB2_1: @ %do.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrw.u32 q0, [r1], #16
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; CHECK-NEXT: vldrw.u32 q1, [r0], #16
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; CHECK-NEXT: vmlava.s32 r12, q1, q0
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; CHECK-NEXT: letp lr, .LBB2_1
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; CHECK-NEXT: @ %bb.2: @ %do.end
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: pop {r7, pc}
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entry:
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%s.0 = phi i32 [ 0, %entry ], [ %5, %do.body ]
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%n.addr.0 = phi i32 [ %n, %entry ], [ %sub, %do.body ]
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%y.addr.0 = phi i32* [ %y, %entry ], [ %add.ptr1, %do.body ]
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%x.addr.0 = phi i32* [ %x, %entry ], [ %add.ptr, %do.body ]
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%0 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.0)
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%1 = bitcast i32* %x.addr.0 to <4 x i32>*
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%2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %1, i32 4, <4 x i1> %0, <4 x i32> zeroinitializer)
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%add.ptr = getelementptr inbounds i32, i32* %x.addr.0, i32 4
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%3 = bitcast i32* %y.addr.0 to <4 x i32>*
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%4 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %3, i32 4, <4 x i1> %0, <4 x i32> zeroinitializer)
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%add.ptr1 = getelementptr inbounds i32, i32* %y.addr.0, i32 4
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%5 = tail call i32 @llvm.arm.mve.vmldava.v4i32(i32 0, i32 0, i32 0, i32 %s.0, <4 x i32> %2, <4 x i32> %4)
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%sub = add nsw i32 %n.addr.0, -4
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%cmp = icmp sgt i32 %n.addr.0, 4
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br i1 %cmp, label %do.body, label %do.end
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do.end: ; preds = %do.body
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ret i32 %5
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}
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define i32 @good2(i32* nocapture readonly %x, i32* nocapture readonly %y, i32 %n) {
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; CHECK-LABEL: good2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: mov r3, r2
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; CHECK-NEXT: cmp r2, #4
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; CHECK-NEXT: it ge
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; CHECK-NEXT: movge r3, #4
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; CHECK-NEXT: subs r3, r2, r3
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; CHECK-NEXT: add.w r12, r3, #3
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; CHECK-NEXT: movs r3, #1
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; CHECK-NEXT: add.w lr, r3, r12, lsr #2
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB3_1: @ %do.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vctp.32 r2
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; CHECK-NEXT: vldrw.u32 q0, [r1], #16
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; CHECK-NEXT: vldrw.u32 q1, [r0], #16
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; CHECK-NEXT: subs r2, #4
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vmlavat.s32 r12, q1, q0
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; CHECK-NEXT: le lr, .LBB3_1
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; CHECK-NEXT: @ %bb.2: @ %do.end
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: pop {r7, pc}
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entry:
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%s.0 = phi i32 [ 0, %entry ], [ %5, %do.body ]
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%n.addr.0 = phi i32 [ %n, %entry ], [ %sub, %do.body ]
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%y.addr.0 = phi i32* [ %y, %entry ], [ %add.ptr1, %do.body ]
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%x.addr.0 = phi i32* [ %x, %entry ], [ %add.ptr, %do.body ]
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%0 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.0)
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%1 = bitcast i32* %x.addr.0 to <4 x i32>*
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%2 = load <4 x i32>, <4 x i32>* %1, align 4
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%add.ptr = getelementptr inbounds i32, i32* %x.addr.0, i32 4
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%3 = bitcast i32* %y.addr.0 to <4 x i32>*
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%4 = load <4 x i32>, <4 x i32>* %3, align 4
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%add.ptr1 = getelementptr inbounds i32, i32* %y.addr.0, i32 4
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%5 = tail call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 0, i32 %s.0, <4 x i32> %2, <4 x i32> %4, <4 x i1> %0)
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%sub = add nsw i32 %n.addr.0, -4
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%cmp = icmp sgt i32 %n.addr.0, 4
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br i1 %cmp, label %do.body, label %do.end
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do.end: ; preds = %do.body
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ret i32 %5
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}
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declare <8 x i1> @llvm.arm.mve.vctp16(i32)
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declare { <8 x i16>, <8 x i16> } @llvm.arm.mve.vld2q.v8i16.p0i16(i16*)
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declare <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>)
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declare <8 x i16> @llvm.arm.mve.qadd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>)
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declare <8 x i16> @llvm.arm.mve.shr.imm.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>, <8 x i16>)
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declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
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declare i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32, i32, i32, i32, <4 x i32>, <4 x i32>, <4 x i1>)
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declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
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declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #2
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declare i32 @llvm.arm.mve.vmldava.v4i32(i32, i32, i32, i32, <4 x i32>, <4 x i32>) #1
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