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[RISCV] Remove a ComputeNumSignBits call from an isel special case. 

Only isel (and (srl (sexti32 Y), c2), c1) -> (srliw (sraiw Y, 31), c3 - 32)
when there is a sext_inreg present. Don't both checking for Y
having 32 sign bits.
This commit is contained in:
Craig Topper 2022-02-04 23:16:36 -08:00
parent 070bc9c1fb
commit 5f35009996
1 changed files with 3 additions and 3 deletions
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6
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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@ -734,11 +734,11 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
//
// This pattern occurs when (i32 (srl (sra 31), c3 - 32)) is type
// legalized and goes through DAG combine.
SDValue Y;
if (C2 >= 32 && (C3 - C2) == 1 && N0.hasOneUse() &&
selectSExti32(X, Y)) {
X.getOpcode() == ISD::SIGN_EXTEND_INREG &&
cast<VTSDNode>(X.getOperand(1))->getVT() == MVT::i32) {
SDNode *SRAIW =
CurDAG->getMachineNode(RISCV::SRAIW, DL, XLenVT, Y,
CurDAG->getMachineNode(RISCV::SRAIW, DL, XLenVT, X.getOperand(0),
CurDAG->getTargetConstant(31, DL, XLenVT));
SDNode *SRLIW = CurDAG->getMachineNode(
RISCV::SRLIW, DL, XLenVT, SDValue(SRAIW, 0),