forked from OSchip/llvm-project
Use a SetTheory instance to expand register lists in register classes.
This prepares tablegen to compute register lists from set theoretic dag expressions. This doesn't really make any difference as long as Target.td still declares RegisterClass::MemberList as [Register]. llvm-svn: 133043
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@ -172,9 +172,9 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
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}
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assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!");
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Elements = R->getValueAsListOfDefs("MemberList");
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for (unsigned i = 0, e = Elements.size(); i != e; ++i)
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Members.insert(RegBank.getReg(Elements[i]));
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Elements = RegBank.getSets().expand(R);
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for (unsigned i = 0, e = Elements->size(); i != e; ++i)
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Members.insert(RegBank.getReg((*Elements)[i]));
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// SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
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ListInit *SRC = R->getValueAsListInit("SubRegClasses");
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@ -240,6 +240,9 @@ const std::string &CodeGenRegisterClass::getName() const {
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//===----------------------------------------------------------------------===//
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CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
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// Configure register Sets to understand register classes.
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Sets.addFieldExpander("RegisterClass", "MemberList");
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// Read in the user-defined (named) sub-register indices.
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// More indices will be synthesized later.
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SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
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@ -16,6 +16,7 @@
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#define CODEGEN_REGISTERS_H
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#include "Record.h"
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#include "SetTheory.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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@ -84,7 +85,7 @@ namespace llvm {
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class CodeGenRegisterClass {
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CodeGenRegister::Set Members;
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std::vector<Record*> Elements;
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const std::vector<Record*> *Elements;
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public:
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Record *TheDef;
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std::string Namespace;
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@ -125,7 +126,7 @@ namespace llvm {
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// Returns an ordered list of class members.
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// The order of registers is the same as in the .td file.
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ArrayRef<Record*> getOrder() const {
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return Elements;
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return *Elements;
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}
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CodeGenRegisterClass(CodeGenRegBank&, Record *R);
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@ -135,6 +136,8 @@ namespace llvm {
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// them.
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class CodeGenRegBank {
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RecordKeeper &Records;
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SetTheory Sets;
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std::vector<Record*> SubRegIndices;
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unsigned NumNamedIndices;
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std::vector<CodeGenRegister> Registers;
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@ -154,6 +157,8 @@ namespace llvm {
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public:
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CodeGenRegBank(RecordKeeper&);
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SetTheory &getSets() { return Sets; }
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// Sub-register indices. The first NumNamedIndices are defined by the user
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// in the .td files. The rest are synthesized such that all sub-registers
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// have a unique name.
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