forked from OSchip/llvm-project
[SelectionDAG] Disallow indirect "i" constraint
This allows us to delete InlineAsm::Constraint_i workarounds in SelectionDAGISel::SelectInlineAsmMemoryOperand overrides and TargetLowering::getInlineAsmMemConstraint overrides. They were introduced to X86 in r237517 to prevent crashes for constraints like "=*imr". They were later copied to other targets.
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@ -3949,9 +3949,7 @@ public:
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StringRef Constraint, MVT VT) const;
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virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
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if (ConstraintCode == "i")
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return InlineAsm::Constraint_i;
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else if (ConstraintCode == "m")
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if (ConstraintCode == "m")
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return InlineAsm::Constraint_m;
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return InlineAsm::Constraint_Unknown;
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}
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@ -4498,6 +4498,12 @@ static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
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TargetLowering::ConstraintType CType =
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TLI.getConstraintType(OpInfo.Codes[i]);
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// Indirect 'other' or 'immediate' constraints are not allowed.
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if (OpInfo.isIndirect && !(CType == TargetLowering::C_Memory ||
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CType == TargetLowering::C_Register ||
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CType == TargetLowering::C_RegisterClass))
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continue;
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// If this is an 'other' or 'immediate' constraint, see if the operand is
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// valid for it. For example, on X86 we might have an 'rI' constraint. If
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// the operand is an integer in the range [0..31] we want to use I (saving a
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@ -304,7 +304,6 @@ bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
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switch(ConstraintID) {
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default:
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llvm_unreachable("Unexpected asm memory constraint");
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case InlineAsm::Constraint_i:
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case InlineAsm::Constraint_m:
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case InlineAsm::Constraint_Q:
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// We need to make sure that this one operand does not end up in XZR, thus
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@ -5047,10 +5047,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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switch(ConstraintID) {
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default:
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llvm_unreachable("Unexpected asm memory constraint");
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case InlineAsm::Constraint_i:
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// FIXME: It seems strange that 'i' is needed here since it's supposed to
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// be an immediate and not a memory constraint.
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LLVM_FALLTHROUGH;
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case InlineAsm::Constraint_m:
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case InlineAsm::Constraint_o:
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case InlineAsm::Constraint_Q:
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@ -916,7 +916,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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switch (ConstraintID) {
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default:
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return true;
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case InlineAsm::Constraint_i:
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case InlineAsm::Constraint_o: // Offsetable.
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case InlineAsm::Constraint_v: // Not offsetable.
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case InlineAsm::Constraint_m: // Memory.
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@ -314,7 +314,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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switch(ConstraintID) {
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default:
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llvm_unreachable("Unexpected asm memory constraint");
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case InlineAsm::Constraint_i:
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case InlineAsm::Constraint_m:
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case InlineAsm::Constraint_R:
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case InlineAsm::Constraint_ZC:
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@ -1282,10 +1282,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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default:
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llvm_unreachable("Unexpected asm memory constraint");
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// All memory constraints can at least accept raw pointers.
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case InlineAsm::Constraint_i:
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OutOps.push_back(Op);
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OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
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return false;
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case InlineAsm::Constraint_m:
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case InlineAsm::Constraint_o:
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if (selectAddrRegImm16(Op, Base, Offset)) {
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@ -310,7 +310,6 @@ namespace {
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errs() << "ConstraintID: " << ConstraintID << "\n";
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llvm_unreachable("Unexpected asm memory constraint");
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case InlineAsm::Constraint_es:
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case InlineAsm::Constraint_i:
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case InlineAsm::Constraint_m:
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case InlineAsm::Constraint_o:
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case InlineAsm::Constraint_Q:
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@ -173,7 +173,6 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
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bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
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const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
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switch (ConstraintID) {
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case InlineAsm::Constraint_i:
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case InlineAsm::Constraint_m:
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// We just support simple memory operands that have a single address
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// operand and need no special handling.
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@ -380,7 +380,6 @@ SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
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SDValue Op0, Op1;
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switch (ConstraintID) {
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default: return true;
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case InlineAsm::Constraint_i:
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case InlineAsm::Constraint_o:
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case InlineAsm::Constraint_m: // memory
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if (!SelectADDRrr(Op, Op0, Op1))
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@ -218,7 +218,6 @@ void WebAssemblyDAGToDAGISel::Select(SDNode *Node) {
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bool WebAssemblyDAGToDAGISel::SelectInlineAsmMemoryOperand(
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const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
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switch (ConstraintID) {
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case InlineAsm::Constraint_i:
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case InlineAsm::Constraint_m:
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// We just support simple memory operands that just have a single address
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// operand and need no special handling.
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@ -5259,10 +5259,6 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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switch (ConstraintID) {
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default:
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llvm_unreachable("Unexpected asm memory constraint");
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case InlineAsm::Constraint_i:
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// FIXME: It seems strange that 'i' is needed here since it's supposed to
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// be an immediate and not a memory constraint.
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LLVM_FALLTHROUGH;
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case InlineAsm::Constraint_o: // offsetable ??
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case InlineAsm::Constraint_v: // not offsetable ??
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case InlineAsm::Constraint_m: // memory
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@ -976,9 +976,7 @@ namespace llvm {
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unsigned
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getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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if (ConstraintCode == "i")
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return InlineAsm::Constraint_i;
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else if (ConstraintCode == "o")
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if (ConstraintCode == "o")
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return InlineAsm::Constraint_o;
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else if (ConstraintCode == "v")
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return InlineAsm::Constraint_v;
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