forked from OSchip/llvm-project
AMDGPU/SI: Fix encoding of flat instructions on VI
Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15735 llvm-svn: 256360
This commit is contained in:
Tom Stellard
parent
04ec5bfad8
commit
5ebdfbe562
|
|
@ -277,9 +277,14 @@ def isSICI : Predicate<
|
|||
"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
|
||||
>, AssemblerPredicate<"FeatureGCN1Encoding">;
|
||||
|
||||
def isVI : Predicate <
|
||||
"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
|
||||
AssemblerPredicate<"FeatureGCN3Encoding">;
|
||||
|
||||
class PredicateControl {
|
||||
Predicate SubtargetPredicate;
|
||||
Predicate SIAssemblerPredicate = isSICI;
|
||||
Predicate VIAssemblerPredicate = isVI;
|
||||
list<Predicate> AssemblerPredicates = [];
|
||||
Predicate AssemblerPredicate = TruePredicate;
|
||||
list<Predicate> OtherPredicates = [];
|
||||
|
|
|
|||
|
|
@ -116,69 +116,154 @@ defm BUFFER_WBINVL1_VOL : MUBUF_Invalidate <mubuf<0x70, 0x3f>,
|
|||
// Flat Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x8, "flat_load_ubyte", VGPR_32>;
|
||||
def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x9, "flat_load_sbyte", VGPR_32>;
|
||||
def FLAT_LOAD_USHORT : FLAT_Load_Helper <0xa, "flat_load_ushort", VGPR_32>;
|
||||
def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0xb, "flat_load_sshort", VGPR_32>;
|
||||
def FLAT_LOAD_DWORD : FLAT_Load_Helper <0xc, "flat_load_dword", VGPR_32>;
|
||||
def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0xd, "flat_load_dwordx2", VReg_64>;
|
||||
def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0xe, "flat_load_dwordx4", VReg_128>;
|
||||
def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0xf, "flat_load_dwordx3", VReg_96>;
|
||||
def FLAT_STORE_BYTE : FLAT_Store_Helper <0x18, "flat_store_byte", VGPR_32>;
|
||||
def FLAT_STORE_SHORT : FLAT_Store_Helper <0x1a, "flat_store_short", VGPR_32>;
|
||||
def FLAT_STORE_DWORD : FLAT_Store_Helper <0x1c, "flat_store_dword", VGPR_32>;
|
||||
def FLAT_STORE_DWORDX2 : FLAT_Store_Helper <
|
||||
0x1d, "flat_store_dwordx2", VReg_64
|
||||
defm FLAT_LOAD_UBYTE : FLAT_Load_Helper <
|
||||
flat<0x8, 0x10>, "flat_load_ubyte", VGPR_32
|
||||
>;
|
||||
def FLAT_STORE_DWORDX4 : FLAT_Store_Helper <
|
||||
0x1e, "flat_store_dwordx4", VReg_128
|
||||
defm FLAT_LOAD_SBYTE : FLAT_Load_Helper <
|
||||
flat<0x9, 0x11>, "flat_load_sbyte", VGPR_32
|
||||
>;
|
||||
def FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
|
||||
0x1f, "flat_store_dwordx3", VReg_96
|
||||
defm FLAT_LOAD_USHORT : FLAT_Load_Helper <
|
||||
flat<0xa, 0x12>, "flat_load_ushort", VGPR_32
|
||||
>;
|
||||
defm FLAT_LOAD_SSHORT : FLAT_Load_Helper <
|
||||
flat<0xb, 0x13>, "flat_load_sshort", VGPR_32>
|
||||
;
|
||||
defm FLAT_LOAD_DWORD : FLAT_Load_Helper <
|
||||
flat<0xc, 0x14>, "flat_load_dword", VGPR_32
|
||||
>;
|
||||
defm FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <
|
||||
flat<0xd, 0x15>, "flat_load_dwordx2", VReg_64
|
||||
>;
|
||||
defm FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <
|
||||
flat<0xe, 0x17>, "flat_load_dwordx4", VReg_128
|
||||
>;
|
||||
defm FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <
|
||||
flat<0xf, 0x16>, "flat_load_dwordx3", VReg_96
|
||||
>;
|
||||
defm FLAT_STORE_BYTE : FLAT_Store_Helper <
|
||||
flat<0x18>, "flat_store_byte", VGPR_32
|
||||
>;
|
||||
defm FLAT_STORE_SHORT : FLAT_Store_Helper <
|
||||
flat <0x1a>, "flat_store_short", VGPR_32
|
||||
>;
|
||||
defm FLAT_STORE_DWORD : FLAT_Store_Helper <
|
||||
flat<0x1c>, "flat_store_dword", VGPR_32
|
||||
>;
|
||||
defm FLAT_STORE_DWORDX2 : FLAT_Store_Helper <
|
||||
flat<0x1d>, "flat_store_dwordx2", VReg_64
|
||||
>;
|
||||
defm FLAT_STORE_DWORDX4 : FLAT_Store_Helper <
|
||||
flat<0x1e, 0x1f>, "flat_store_dwordx4", VReg_128
|
||||
>;
|
||||
defm FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
|
||||
flat<0x1f, 0x1e>, "flat_store_dwordx3", VReg_96
|
||||
>;
|
||||
defm FLAT_ATOMIC_SWAP : FLAT_ATOMIC <
|
||||
flat<0x30, 0x40>, "flat_atomic_swap", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_SWAP : FLAT_ATOMIC <0x30, "flat_atomic_swap", VGPR_32>;
|
||||
defm FLAT_ATOMIC_CMPSWAP : FLAT_ATOMIC <
|
||||
0x31, "flat_atomic_cmpswap", VGPR_32, VReg_64
|
||||
flat<0x31, 0x41>, "flat_atomic_cmpswap", VGPR_32, VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_ADD : FLAT_ATOMIC <0x32, "flat_atomic_add", VGPR_32>;
|
||||
defm FLAT_ATOMIC_SUB : FLAT_ATOMIC <0x33, "flat_atomic_sub", VGPR_32>;
|
||||
defm FLAT_ATOMIC_SMIN : FLAT_ATOMIC <0x35, "flat_atomic_smin", VGPR_32>;
|
||||
defm FLAT_ATOMIC_UMIN : FLAT_ATOMIC <0x36, "flat_atomic_umin", VGPR_32>;
|
||||
defm FLAT_ATOMIC_SMAX : FLAT_ATOMIC <0x37, "flat_atomic_smax", VGPR_32>;
|
||||
defm FLAT_ATOMIC_UMAX : FLAT_ATOMIC <0x38, "flat_atomic_umax", VGPR_32>;
|
||||
defm FLAT_ATOMIC_AND : FLAT_ATOMIC <0x39, "flat_atomic_and", VGPR_32>;
|
||||
defm FLAT_ATOMIC_OR : FLAT_ATOMIC <0x3a, "flat_atomic_or", VGPR_32>;
|
||||
defm FLAT_ATOMIC_XOR : FLAT_ATOMIC <0x3b, "flat_atomic_xor", VGPR_32>;
|
||||
defm FLAT_ATOMIC_INC : FLAT_ATOMIC <0x3c, "flat_atomic_inc", VGPR_32>;
|
||||
defm FLAT_ATOMIC_DEC : FLAT_ATOMIC <0x3d, "flat_atomic_dec", VGPR_32>;
|
||||
defm FLAT_ATOMIC_FCMPSWAP : FLAT_ATOMIC <
|
||||
0x3e, "flat_atomic_fcmpswap", VGPR_32, VReg_64
|
||||
defm FLAT_ATOMIC_ADD : FLAT_ATOMIC <
|
||||
flat<0x32, 0x42>, "flat_atomic_add", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_SUB : FLAT_ATOMIC <
|
||||
flat<0x33, 0x43>, "flat_atomic_sub", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_SMIN : FLAT_ATOMIC <
|
||||
flat<0x35, 0x44>, "flat_atomic_smin", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_UMIN : FLAT_ATOMIC <
|
||||
flat<0x36, 0x45>, "flat_atomic_umin", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_SMAX : FLAT_ATOMIC <
|
||||
flat<0x37, 0x46>, "flat_atomic_smax", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_UMAX : FLAT_ATOMIC <
|
||||
flat<0x38, 0x47>, "flat_atomic_umax", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_AND : FLAT_ATOMIC <
|
||||
flat<0x39, 0x48>, "flat_atomic_and", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_OR : FLAT_ATOMIC <
|
||||
flat<0x3a, 0x49>, "flat_atomic_or", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_XOR : FLAT_ATOMIC <
|
||||
flat<0x3b, 0x4a>, "flat_atomic_xor", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_INC : FLAT_ATOMIC <
|
||||
flat<0x3c, 0x4b>, "flat_atomic_inc", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_DEC : FLAT_ATOMIC <
|
||||
flat<0x3d, 0x4c>, "flat_atomic_dec", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_SWAP_X2 : FLAT_ATOMIC <
|
||||
flat<0x50, 0x60>, "flat_atomic_swap_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_FMIN : FLAT_ATOMIC <0x3f, "flat_atomic_fmin", VGPR_32>;
|
||||
defm FLAT_ATOMIC_FMAX : FLAT_ATOMIC <0x40, "flat_atomic_fmax", VGPR_32>;
|
||||
defm FLAT_ATOMIC_SWAP_X2 : FLAT_ATOMIC <0x50, "flat_atomic_swap_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_ATOMIC <
|
||||
0x51, "flat_atomic_cmpswap_x2", VReg_64, VReg_128
|
||||
flat<0x51, 0x61>, "flat_atomic_cmpswap_x2", VReg_64, VReg_128
|
||||
>;
|
||||
defm FLAT_ATOMIC_ADD_X2 : FLAT_ATOMIC <0x52, "flat_atomic_add_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_SUB_X2 : FLAT_ATOMIC <0x53, "flat_atomic_sub_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_SMIN_X2 : FLAT_ATOMIC <0x55, "flat_atomic_smin_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_UMIN_X2 : FLAT_ATOMIC <0x56, "flat_atomic_umin_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_SMAX_X2 : FLAT_ATOMIC <0x57, "flat_atomic_smax_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_UMAX_X2 : FLAT_ATOMIC <0x58, "flat_atomic_umax_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_AND_X2 : FLAT_ATOMIC <0x59, "flat_atomic_and_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_OR_X2 : FLAT_ATOMIC <0x5a, "flat_atomic_or_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_XOR_X2 : FLAT_ATOMIC <0x5b, "flat_atomic_xor_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_INC_X2 : FLAT_ATOMIC <0x5c, "flat_atomic_inc_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_DEC_X2 : FLAT_ATOMIC <0x5d, "flat_atomic_dec_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_ATOMIC <
|
||||
0x5e, "flat_atomic_fcmpswap_x2", VReg_64, VReg_128
|
||||
defm FLAT_ATOMIC_ADD_X2 : FLAT_ATOMIC <
|
||||
flat<0x52, 0x62>, "flat_atomic_add_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_SUB_X2 : FLAT_ATOMIC <
|
||||
flat<0x53, 0x63>, "flat_atomic_sub_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_SMIN_X2 : FLAT_ATOMIC <
|
||||
flat<0x55, 0x64>, "flat_atomic_smin_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_UMIN_X2 : FLAT_ATOMIC <
|
||||
flat<0x56, 0x65>, "flat_atomic_umin_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_SMAX_X2 : FLAT_ATOMIC <
|
||||
flat<0x57, 0x66>, "flat_atomic_smax_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_UMAX_X2 : FLAT_ATOMIC <
|
||||
flat<0x58, 0x67>, "flat_atomic_umax_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_AND_X2 : FLAT_ATOMIC <
|
||||
flat<0x59, 0x68>, "flat_atomic_and_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_OR_X2 : FLAT_ATOMIC <
|
||||
flat<0x5a, 0x69>, "flat_atomic_or_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_XOR_X2 : FLAT_ATOMIC <
|
||||
flat<0x5b, 0x6a>, "flat_atomic_xor_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_INC_X2 : FLAT_ATOMIC <
|
||||
flat<0x5c, 0x6b>, "flat_atomic_inc_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_DEC_X2 : FLAT_ATOMIC <
|
||||
flat<0x5d, 0x6c>, "flat_atomic_dec_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_FMIN_X2 : FLAT_ATOMIC <0x5f, "flat_atomic_fmin_x2", VReg_64>;
|
||||
defm FLAT_ATOMIC_FMAX_X2 : FLAT_ATOMIC <0x60, "flat_atomic_fmax_x2", VReg_64>;
|
||||
|
||||
} // End SubtargetPredicate = isCIVI
|
||||
|
||||
// CI Only flat instructions
|
||||
|
||||
let SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst in {
|
||||
|
||||
defm FLAT_ATOMIC_FCMPSWAP : FLAT_ATOMIC <
|
||||
flat<0x3e>, "flat_atomic_fcmpswap", VGPR_32, VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_FMIN : FLAT_ATOMIC <
|
||||
flat<0x3f>, "flat_atomic_fmin", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_FMAX : FLAT_ATOMIC <
|
||||
flat<0x40>, "flat_atomic_fmax", VGPR_32
|
||||
>;
|
||||
defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_ATOMIC <
|
||||
flat<0x5e>, "flat_atomic_fcmpswap_x2", VReg_64, VReg_128
|
||||
>;
|
||||
defm FLAT_ATOMIC_FMIN_X2 : FLAT_ATOMIC <
|
||||
flat<0x5f>, "flat_atomic_fmin_x2", VReg_64
|
||||
>;
|
||||
defm FLAT_ATOMIC_FMAX_X2 : FLAT_ATOMIC <
|
||||
flat<0x60>, "flat_atomic_fmax_x2", VReg_64
|
||||
>;
|
||||
|
||||
} // End let SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Flat Patterns
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -11,9 +11,6 @@ def isCI : Predicate<"Subtarget->getGeneration() "
|
|||
def isCIOnly : Predicate<"Subtarget->getGeneration() =="
|
||||
"AMDGPUSubtarget::SEA_ISLANDS">,
|
||||
AssemblerPredicate <"FeatureSeaIslands">;
|
||||
def isVI : Predicate <
|
||||
"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
|
||||
AssemblerPredicate<"FeatureGCN3Encoding">;
|
||||
|
||||
def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
|
||||
|
||||
|
|
@ -2557,48 +2554,104 @@ multiclass MUBUF_Invalidate <mubuf op, string opName, SDPatternOperator node> {
|
|||
} // End hasSideEffects = 1, mayStore = 1, AsmMatchConverter = ""
|
||||
}
|
||||
|
||||
class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
|
||||
FLAT <op, (outs regClass:$vdst),
|
||||
(ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
|
||||
asm#" $vdst, $addr"#"$glc"#"$slc"#"$tfe", []> {
|
||||
let data = 0;
|
||||
let mayLoad = 1;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// FLAT classes
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class flat <bits<7> ci, bits<7> vi = ci> {
|
||||
field bits<7> CI = ci;
|
||||
field bits<7> VI = vi;
|
||||
}
|
||||
|
||||
class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
|
||||
FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr,
|
||||
glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
|
||||
name#" $data, $addr"#"$glc"#"$slc"#"$tfe",
|
||||
[]> {
|
||||
|
||||
let mayLoad = 0;
|
||||
let mayStore = 1;
|
||||
|
||||
// Encoding
|
||||
let vdst = 0;
|
||||
class FLAT_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
|
||||
FLAT <0, outs, ins, "", pattern>,
|
||||
SIMCInstr<opName, SISubtarget.NONE> {
|
||||
let isPseudo = 1;
|
||||
let isCodeGenOnly = 1;
|
||||
}
|
||||
|
||||
multiclass FLAT_ATOMIC <bits<7> op, string name, RegisterClass vdst_rc,
|
||||
RegisterClass data_rc = vdst_rc> {
|
||||
class FLAT_Real_ci <bits<7> op, string opName, dag outs, dag ins, string asm> :
|
||||
FLAT <op, outs, ins, asm, []>,
|
||||
SIMCInstr<opName, SISubtarget.SI> {
|
||||
let AssemblerPredicate = isCIOnly;
|
||||
}
|
||||
|
||||
let mayLoad = 1, mayStore = 1 in {
|
||||
def "" : FLAT <op, (outs),
|
||||
(ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
|
||||
tfe_flat_atomic:$tfe),
|
||||
name#" $addr, $data"#"$slc"#"$tfe", []>,
|
||||
AtomicNoRet <NAME, 0> {
|
||||
let glc = 0;
|
||||
let vdst = 0;
|
||||
}
|
||||
class FLAT_Real_vi <bits<7> op, string opName, dag outs, dag ins, string asm> :
|
||||
FLAT <op, outs, ins, asm, []>,
|
||||
SIMCInstr<opName, SISubtarget.VI> {
|
||||
let AssemblerPredicate = VIAssemblerPredicate;
|
||||
}
|
||||
|
||||
def _RTN : FLAT <op, (outs vdst_rc:$vdst),
|
||||
(ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
|
||||
tfe_flat_atomic:$tfe),
|
||||
name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>,
|
||||
AtomicNoRet <NAME, 1> {
|
||||
let glc = 1;
|
||||
let hasPostISelHook = 1;
|
||||
}
|
||||
multiclass FLAT_AtomicRet_m <flat op, dag outs, dag ins, string asm,
|
||||
list<dag> pattern> {
|
||||
def "" : FLAT_Pseudo <NAME#"_RTN", outs, ins, pattern>,
|
||||
AtomicNoRet <NAME, 1>;
|
||||
|
||||
def _ci : FLAT_Real_ci <op.CI, NAME#"_RTN", outs, ins, asm>;
|
||||
|
||||
def _vi : FLAT_Real_vi <op.VI, NAME#"_RTN", outs, ins, asm>;
|
||||
}
|
||||
|
||||
multiclass FLAT_Load_Helper <flat op, string asm_name,
|
||||
RegisterClass regClass,
|
||||
dag outs = (outs regClass:$vdst),
|
||||
dag ins = (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
|
||||
string asm = asm_name#" $vdst, $addr"#"$glc"#"$slc"#"$tfe"> {
|
||||
|
||||
let data = 0, mayLoad = 1 in {
|
||||
|
||||
def "" : FLAT_Pseudo <NAME, outs, ins, []>;
|
||||
|
||||
def _ci : FLAT_Real_ci <op.CI, NAME, outs, ins, asm>;
|
||||
|
||||
def _vi : FLAT_Real_vi <op.VI, NAME, outs, ins, asm>;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass FLAT_Store_Helper <flat op, string asm_name,
|
||||
RegisterClass vdataClass,
|
||||
dag outs = (outs),
|
||||
dag ins = (ins vdataClass:$data, VReg_64:$addr, glc_flat:$glc,
|
||||
slc_flat:$slc, tfe_flat:$tfe),
|
||||
string asm = asm_name#" $data, $addr"#"$glc"#"$slc"#"$tfe"> {
|
||||
|
||||
let mayLoad = 0, mayStore = 1, vdst = 0 in {
|
||||
|
||||
def "" : FLAT_Pseudo <NAME, outs, ins, []>;
|
||||
|
||||
def _ci : FLAT_Real_ci <op.CI, NAME, outs, ins, asm>;
|
||||
|
||||
def _vi : FLAT_Real_vi <op.VI, NAME, outs, ins, asm>;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass FLAT_ATOMIC <flat op, string asm_name, RegisterClass vdst_rc,
|
||||
RegisterClass data_rc = vdst_rc,
|
||||
dag outs_noret = (outs),
|
||||
string asm_noret = asm_name#" $addr, $data"#"$slc"#"$tfe"> {
|
||||
|
||||
let mayLoad = 1, mayStore = 1, glc = 0, vdst = 0 in {
|
||||
def "" : FLAT_Pseudo <NAME, outs_noret,
|
||||
(ins VReg_64:$addr, data_rc:$data,
|
||||
slc_flat_atomic:$slc, tfe_flat_atomic:$tfe), []>,
|
||||
AtomicNoRet <NAME, 0>;
|
||||
|
||||
def _ci : FLAT_Real_ci <op.CI, NAME, outs_noret,
|
||||
(ins VReg_64:$addr, data_rc:$data,
|
||||
slc_flat_atomic:$slc, tfe_flat_atomic:$tfe),
|
||||
asm_noret>;
|
||||
|
||||
def _vi : FLAT_Real_vi <op.VI, NAME, outs_noret,
|
||||
(ins VReg_64:$addr, data_rc:$data,
|
||||
slc_flat_atomic:$slc, tfe_flat_atomic:$tfe),
|
||||
asm_noret>;
|
||||
}
|
||||
|
||||
let glc = 1, hasPostISelHook = 1 in {
|
||||
defm _RTN : FLAT_AtomicRet_m <op, (outs vdst_rc:$vdst),
|
||||
(ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
|
||||
tfe_flat_atomic:$tfe),
|
||||
asm_name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,143 +1,162 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=CI
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=CIVI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=VI
|
||||
|
||||
// FIXME: These instructions give an 'invalid operand' error on SI and should
|
||||
// instead be reporting an 'instruction not supported' error.
|
||||
// FIXME: For missing instruction the error message is:
|
||||
// error: too few operands for instruction
|
||||
// It should be:
|
||||
// error: instruction not supported on this GPU
|
||||
//
|
||||
|
||||
// XUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=NOVI
|
||||
// XUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI
|
||||
// XUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOVI
|
||||
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Operands
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
flat_load_dword v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] glc slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] glc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] glc slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] glc tfe slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] slc glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] slc glc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] slc tfe glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x80,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] tfe glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x31,0xdc,0x03,0x00,0x80,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] tfe slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x32,0xdc,0x03,0x00,0x80,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] tfe glc slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] tfe slc glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x33,0xdc,0x03,0x00,0x80,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
|
||||
|
||||
flat_store_dword v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] glc slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] glc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] glc slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] glc tfe slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] slc glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] slc glc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] slc tfe glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] tfe glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x71,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] tfe slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x72,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] tfe glc slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4] tfe slc glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x73,0xdc,0x03,0x01,0x80,0x00]
|
||||
|
||||
// FIXME: For atomic instructions, glc must be placed immediately following
|
||||
|
|
@ -151,327 +170,406 @@ flat_store_dword v1, v[3:4] tfe slc glc
|
|||
// flat_atomic_add v1, v[3:4], v5 tfe slc glc
|
||||
|
||||
flat_atomic_add v1 v[3:4], v5 glc slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_add v1 v[3:4], v5 glc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v1, v[3:4], v5 glc tfe ; encoding: [0x00,0x00,0xc9,0xdc,0x03,0x05,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add v1, v[3:4], v5 glc tfe ; encoding: [0x00,0x00,0xc9,0xdc,0x03,0x05,0x80,0x01]
|
||||
// VI: flat_atomic_add v1, v[3:4], v5 glc tfe ; encoding: [0x00,0x00,0x09,0xdd,0x03,0x05,0x80,0x01]
|
||||
|
||||
flat_atomic_add v1 v[3:4], v5 glc slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01]
|
||||
// VI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x80,0x01]
|
||||
|
||||
flat_atomic_add v1 v[3:4], v5 glc tfe slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x80,0x01]
|
||||
// VI: flat_atomic_add v1, v[3:4], v5 glc slc tfe ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x80,0x01]
|
||||
|
||||
flat_atomic_add v[3:4], v5 slc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v[3:4], v5 slc ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add v[3:4], v5 slc ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_add v[3:4], v5 slc ; encoding: [0x00,0x00,0x0a,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_add v[3:4], v5 slc tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v[3:4], v5 slc tfe ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x80,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add v[3:4], v5 slc tfe ; encoding: [0x00,0x00,0xca,0xdc,0x03,0x05,0x80,0x00]
|
||||
// VI: flat_atomic_add v[3:4], v5 slc tfe ; encoding: [0x00,0x00,0x0a,0xdd,0x03,0x05,0x80,0x00]
|
||||
|
||||
flat_atomic_add v[3:4], v5 tfe
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v[3:4], v5 tfe ; encoding: [0x00,0x00,0xc8,0xdc,0x03,0x05,0x80,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add v[3:4], v5 tfe ; encoding: [0x00,0x00,0xc8,0xdc,0x03,0x05,0x80,0x00]
|
||||
// VI: flat_atomic_add v[3:4], v5 tfe ; encoding: [0x00,0x00,0x08,0xdd,0x03,0x05,0x80,0x00]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
flat_load_ubyte v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_ubyte v1, v[3:4] ; encoding: [0x00,0x00,0x20,0xdc,0x03,0x00,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_ubyte v1, v[3:4] ; encoding: [0x00,0x00,0x20,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VI: flat_load_ubyte v1, v[3:4] ; encoding: [0x00,0x00,0x40,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_sbyte v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_sbyte v1, v[3:4] ; encoding: [0x00,0x00,0x24,0xdc,0x03,0x00,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_sbyte v1, v[3:4] ; encoding: [0x00,0x00,0x24,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VI: flat_load_sbyte v1, v[3:4] ; encoding: [0x00,0x00,0x44,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_ushort v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_ushort v1, v[3:4] ; encoding: [0x00,0x00,0x28,0xdc,0x03,0x00,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_ushort v1, v[3:4] ; encoding: [0x00,0x00,0x28,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VI: flat_load_ushort v1, v[3:4] ; encoding: [0x00,0x00,0x48,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_sshort v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_sshort v1, v[3:4] ; encoding: [0x00,0x00,0x2c,0xdc,0x03,0x00,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_sshort v1, v[3:4] ; encoding: [0x00,0x00,0x2c,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VI: flat_load_sshort v1, v[3:4] ; encoding: [0x00,0x00,0x4c,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dwordx2 v[1:2], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x00,0x34,0xdc,0x03,0x00,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x00,0x34,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VI: flat_load_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x00,0x54,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dwordx4 v[5:8], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x38,0xdc,0x03,0x00,0x00,0x05]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x38,0xdc,0x03,0x00,0x00,0x05]
|
||||
// VI: flat_load_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x5c,0xdc,0x03,0x00,0x00,0x05]
|
||||
|
||||
flat_load_dwordx3 v[5:7], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_load_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x3c,0xdc,0x03,0x00,0x00,0x05]
|
||||
// NOSI: error:
|
||||
// CI: flat_load_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x3c,0xdc,0x03,0x00,0x00,0x05]
|
||||
// VI: flat_load_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x58,0xdc,0x03,0x00,0x00,0x05]
|
||||
|
||||
flat_store_byte v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_byte v1, v[3:4] ; encoding: [0x00,0x00,0x60,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_short v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_short v1, v[3:4] ; encoding: [0x00,0x00,0x68,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dword v1, v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dword v1, v[3:4] ; encoding: [0x00,0x00,0x70,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dwordx2 v[1:2], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CIVI: flat_store_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x00,0x74,0xdc,0x03,0x01,0x00,0x00]
|
||||
|
||||
flat_store_dwordx4 v[5:8], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x78,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_store_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x78,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_store_dwordx4 v[5:8], v[3:4] ; encoding: [0x00,0x00,0x7c,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_store_dwordx3 v[5:7], v[3:4]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_store_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x7c,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_store_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x7c,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_store_dwordx3 v[5:7], v[3:4] ; encoding: [0x00,0x00,0x78,0xdc,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_swap v[3:4], v5 ; encoding: [0x00,0x00,0xc0,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_swap v[3:4], v5 ; encoding: [0x00,0x00,0xc0,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_swap v[3:4], v5 ; encoding: [0x00,0x00,0x00,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_swap v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_swap v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xc1,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_swap v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xc1,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_swap v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x01,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_cmpswap v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_cmpswap v[3:4], v[5:6] ; encoding: [0x00,0x00,0xc4,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_cmpswap v[3:4], v[5:6] ; encoding: [0x00,0x00,0xc4,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_cmpswap v[3:4], v[5:6] ; encoding: [0x00,0x00,0x04,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap v1, v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_cmpswap v1, v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0xc5,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_cmpswap v1, v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0xc5,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_cmpswap v1, v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x05,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_add v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v[3:4], v5 ; encoding: [0x00,0x00,0xc8,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add v[3:4], v5 ; encoding: [0x00,0x00,0xc8,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_add v[3:4], v5 ; encoding: [0x00,0x00,0x08,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_add v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xc9,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xc9,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_add v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x09,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_sub v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_sub v[3:4], v5 ; encoding: [0x00,0x00,0xcc,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_sub v[3:4], v5 ; encoding: [0x00,0x00,0xcc,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_sub v[3:4], v5 ; encoding: [0x00,0x00,0x0c,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_sub v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_sub v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xcd,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_sub v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xcd,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_sub v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x0d,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_smin v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smin v[3:4], v5 ; encoding: [0x00,0x00,0xd4,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_smin v[3:4], v5 ; encoding: [0x00,0x00,0xd4,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_smin v[3:4], v5 ; encoding: [0x00,0x00,0x10,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_smin v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xd5,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_smin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xd5,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_smin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x11,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_umin v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umin v[3:4], v5 ; encoding: [0x00,0x00,0xd8,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_umin v[3:4], v5 ; encoding: [0x00,0x00,0xd8,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_umin v[3:4], v5 ; encoding: [0x00,0x00,0x14,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_umin v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xd9,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_umin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xd9,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_umin v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x15,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_smax v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smax v[3:4], v5 ; encoding: [0x00,0x00,0xdc,0xdc,0x03,0x05,0x00,0x00]
|
||||
flat_atomic_smax v[3:4], v5,
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_smax v[3:4], v5 ; encoding: [0x00,0x00,0xdc,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_smax v[3:4], v5 ; encoding: [0x00,0x00,0x18,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_smax v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xdd,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_smax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xdd,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_smax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x19,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_umax v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umax v[3:4], v5 ; encoding: [0x00,0x00,0xe0,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_umax v[3:4], v5 ; encoding: [0x00,0x00,0xe0,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_umax v[3:4], v5 ; encoding: [0x00,0x00,0x1c,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_umax v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe1,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_umax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe1,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_umax v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x1d,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_and v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_and v[3:4], v5 ; encoding: [0x00,0x00,0xe4,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_and v[3:4], v5 ; encoding: [0x00,0x00,0xe4,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_and v[3:4], v5 ; encoding: [0x00,0x00,0x20,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_and v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_and v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe5,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_and v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe5,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_and v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x21,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_or v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_or v[3:4], v5 ; encoding: [0x00,0x00,0xe8,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_or v[3:4], v5 ; encoding: [0x00,0x00,0xe8,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_or v[3:4], v5 ; encoding: [0x00,0x00,0x24,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_or v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_or v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe9,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_or v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xe9,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_or v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x25,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_xor v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_xor v[3:4], v5 ; encoding: [0x00,0x00,0xec,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_xor v[3:4], v5 ; encoding: [0x00,0x00,0xec,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_xor v[3:4], v5 ; encoding: [0x00,0x00,0x28,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_xor v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_xor v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xed,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_xor v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xed,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_xor v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x29,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_inc v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_inc v[3:4], v5 ; encoding: [0x00,0x00,0xf0,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_inc v[3:4], v5 ; encoding: [0x00,0x00,0xf0,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_inc v[3:4], v5 ; encoding: [0x00,0x00,0x2c,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_inc v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_inc v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xf1,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_inc v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xf1,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_inc v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x2d,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_dec v[3:4], v5
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_dec v[3:4], v5 ; encoding: [0x00,0x00,0xf4,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_dec v[3:4], v5 ; encoding: [0x00,0x00,0xf4,0xdc,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_dec v[3:4], v5 ; encoding: [0x00,0x00,0x30,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_dec v1, v[3:4], v5 glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_dec v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xf5,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_dec v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0xf5,0xdc,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_dec v1, v[3:4], v5 glc ; encoding: [0x00,0x00,0x31,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_fcmpswap v[3:4], v[5:6]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_fcmpswap v[3:4], v[5:6] ; encoding: [0x00,0x00,0xf8,0xdc,0x03,0x05,0x00,0x00]
|
||||
// NOVI: error:
|
||||
|
||||
flat_atomic_fcmpswap v1, v[3:4], v[5:6] glc
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_fcmpswap v1, v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0xf9,0xdc,0x03,0x05,0x00,0x01]
|
||||
// NOVI: error:
|
||||
|
||||
flat_atomic_swap_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_swap_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x40,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_swap_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x40,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_swap_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x80,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_swap_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_swap_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x41,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_swap_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x41,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_swap_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x81,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[3:4], v[5:8]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_cmpswap_x2 v[3:4], v[5:8] ; encoding: [0x00,0x00,0x44,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_cmpswap_x2 v[3:4], v[5:8] ; encoding: [0x00,0x00,0x44,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_cmpswap_x2 v[3:4], v[5:8] ; encoding: [0x00,0x00,0x84,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_cmpswap_x2 v[1:2], v[3:4], v[5:8] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_cmpswap_x2 v[1:2], v[3:4], v[5:8] glc ; encoding: [0x00,0x00,0x45,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_cmpswap_x2 v[1:2], v[3:4], v[5:8] glc ; encoding: [0x00,0x00,0x45,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_cmpswap_x2 v[1:2], v[3:4], v[5:8] glc ; encoding: [0x00,0x00,0x85,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_add_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x48,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x48,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_add_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x88,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_add_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_add_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x49,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_add_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x49,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_add_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x89,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_sub_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_sub_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x4c,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_sub_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x4c,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_sub_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x8c,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_sub_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_sub_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x4d,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_sub_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x4d,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_sub_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x8d,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_smin_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x54,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_smin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x54,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_smin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x90,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_smin_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x55,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_smin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x55,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_smin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x91,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_umin_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x58,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_umin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x58,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_umin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x94,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x59,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x59,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_umin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x95,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_smax_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x5c,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_smax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x5c,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_smax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x98,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_smax_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_smax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x5d,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_smax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x5d,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_smax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x99,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_umax_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x60,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_umax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x60,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_umax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x9c,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_umax_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_umax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x61,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_umax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x61,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_umax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x9d,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_and_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_and_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x64,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_and_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x64,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_and_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0xa0,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_and_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_and_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x65,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_and_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x65,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_and_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0xa1,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_or_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_or_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x68,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_or_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x68,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_or_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0xa4,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_or_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_or_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x69,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_or_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x69,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_or_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0xa5,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_xor_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_xor_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x6c,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_xor_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x6c,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_xor_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0xa8,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_xor_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_xor_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x6d,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_xor_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x6d,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_xor_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0xa9,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_inc_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_inc_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x70,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_inc_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x70,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_inc_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0xac,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_inc_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_inc_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x71,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_inc_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x71,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_inc_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0xad,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_dec_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_dec_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x74,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_dec_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x74,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VI: flat_atomic_dec_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0xb0,0xdd,0x03,0x05,0x00,0x00]
|
||||
|
||||
flat_atomic_dec_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// CIVI: flat_atomic_dec_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x75,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_dec_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x75,0xdd,0x03,0x05,0x00,0x01]
|
||||
// VI: flat_atomic_dec_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0xb1,0xdd,0x03,0x05,0x00,0x01]
|
||||
|
||||
flat_atomic_fcmpswap_x2 v[3:4], v[5:8]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_fcmpswap_x2 v[3:4], v[5:8] ; encoding: [0x00,0x00,0x78,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: error:
|
||||
|
||||
flat_atomic_fcmpswap_x2 v[1:2], v[3:4], v[5:8] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_fcmpswap_x2 v[1:2], v[3:4], v[5:8] glc ; encoding: [0x00,0x00,0x79,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: error:
|
||||
|
||||
flat_atomic_fmin_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_fmin_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x7c,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: error:
|
||||
|
||||
flat_atomic_fmin_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_fmin_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x7d,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: error:
|
||||
|
||||
flat_atomic_fmax_x2 v[3:4], v[5:6]
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_fmax_x2 v[3:4], v[5:6] ; encoding: [0x00,0x00,0x80,0xdd,0x03,0x05,0x00,0x00]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: error:
|
||||
|
||||
flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc
|
||||
// NOSI: error: instruction not supported on this GPU
|
||||
// NOSI: error:
|
||||
// CI: flat_atomic_fmax_x2 v[1:2], v[3:4], v[5:6] glc ; encoding: [0x00,0x00,0x81,0xdd,0x03,0x05,0x00,0x01]
|
||||
// NOVI: error: instruction not supported on this GPU
|
||||
// NOVI: error:
|
||||
|
|
|
|||
Loading…
Reference in New Issue