forked from OSchip/llvm-project
R600: Add ALUInst bit to tablegen definitions v2
v2: - Remove functions left over from a previous rebase. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185160
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@ -41,7 +41,8 @@ namespace R600_InstFlag {
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OP1 = (1 << 10),
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OP2 = (1 << 11),
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VTX_INST = (1 << 12),
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TEX_INST = (1 << 13)
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TEX_INST = (1 << 13),
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ALU_INST = (1 << 14)
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};
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}
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@ -26,6 +26,7 @@ class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
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bit HasNativeOperands = 0;
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bit VTXInst = 0;
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bit TEXInst = 0;
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bit ALUInst = 0;
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let Namespace = "AMDGPU";
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let OutOperandList = outs;
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@ -47,6 +48,7 @@ class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
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let TSFlags{11} = Op2;
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let TSFlags{12} = VTXInst;
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let TSFlags{13} = TEXInst;
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let TSFlags{14} = ALUInst;
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}
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//===----------------------------------------------------------------------===//
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@ -133,9 +133,7 @@ bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
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bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
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unsigned TargetFlags = get(Opcode).TSFlags;
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return ((TargetFlags & R600_InstFlag::OP1) |
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(TargetFlags & R600_InstFlag::OP2) |
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(TargetFlags & R600_InstFlag::OP3));
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return (TargetFlags & R600_InstFlag::ALU_INST);
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}
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bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
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@ -114,6 +114,7 @@ class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
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let update_pred = 0;
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let HasNativeOperands = 1;
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let Op1 = 1;
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let ALUInst = 1;
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let DisableEncoding = "$literal";
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let UseNamedOperandTable = 1;
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@ -151,6 +152,7 @@ class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
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let HasNativeOperands = 1;
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let Op2 = 1;
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let ALUInst = 1;
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let DisableEncoding = "$literal";
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let UseNamedOperandTable = 1;
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@ -193,6 +195,7 @@ class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
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let DisableEncoding = "$literal";
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let Op3 = 1;
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let UseNamedOperandTable = 1;
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let ALUInst = 1;
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let Inst{31-0} = Word0;
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let Inst{63-32} = Word1;
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